SYNOPSYS USB Search Results

SYNOPSYS USB Result Highlights (5)

Part	Manufacturer	Description	Download
CS-USB3.1TYPC-001M	Amphenol Cables on Demand	Amphenol CS-USB3.1TYPC-001M Amphenol Premium USB 3.1 Gen2 Certified USB Type A-C Cable - USB 3.0 Type A Male to Type C Male [10.0 Gbps SuperSpeed] 1m (3.3ft)	Datasheet
CS-USBAM003.0-001	Amphenol Cables on Demand	Amphenol CS-USBAM003.0-001 Amphenol Premium USB 3.0/3.1 Gen1 Certified USB Type A-A Cable - USB 3.0 Type A Male to Type A Male [5.0 Gbps SuperSpeed] 1m (3.3')	Datasheet
CS-USBAB003.0-002	Amphenol Cables on Demand	Amphenol CS-USBAB003.0-002 Amphenol Premium USB 3.0/3.1 Gen1 Certified USB Type A-B Cable - USB 3.0 Type A Male to Type B Male [5.0 Gbps SuperSpeed] 2m (6.6')	Datasheet
CS-USBAB003.0-001	Amphenol Cables on Demand	Amphenol CS-USBAB003.0-001 Amphenol Premium USB 3.0/3.1 Gen1 Certified USB Type A-B Cable - USB 3.0 Type A Male to Type B Male [5.0 Gbps SuperSpeed] 1m (3.3')	Datasheet
CS-USBAM003.0-002	Amphenol Cables on Demand	Amphenol CS-USBAM003.0-002 Amphenol Premium USB 3.0/3.1 Gen1 Certified USB Type A-A Cable - USB 3.0 Type A Male to Type A Male [5.0 Gbps SuperSpeed] 2m (6.6')	Datasheet

SYNOPSYS USB Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
16V8 Abstract: 20V8 Text: PRESS RELEASE CYPRESS OFFERS SYNOPSYS SOFTWARE SUPPORT FOR FLASH370i CPLDs “Bolt-in Kit” Allows Seamless Integration of Synopsys Tools with Warp Software SAN JOSE, Calif., October 27, 1997 - Cypress Semiconductor Corp. NYSE:CY today announced that users can now utilize CAE software from Synopsys to design with Cypress’s	Original	FLASH370iTM FLASH370i 16V8 20V8	PDF
16V8 Abstract: 20V8 Text: PRESS RELEASE SYNOPSYS’ FPGA EXPRESS  NOW SUPPORTS CYPRESS Ultra37000  CPLDs Gives Seamless Integration of Synopsys Tools with Warp  Software SAN JOSE, Calif., December 15, 1998 - Cypress Semiconductor Corp. NYSE:CY today announced that designers can now use Synopsys’ FPGA Express synthesis tool to design with	Original	Ultra37000TM Ultra37000 Ultra37000, FLASH370i 16V8 20V8	PDF
Untitled Abstract: No abstract text available Text: Press Release SYNOPSYS’ FPGA EXPRESS  NOW SUPPORTS CYPRESS Ultra37000  CPLDs Gives Seamless Integration of Synopsys Tools with Warp  Software SAN JOSE, Calif., December 15, 1998 - Cypress Semiconductor Corp. NYSE:CY today announced that designers	Original	Ultra37000 Ultra37000, FLASH370i	PDF
hapstrak Abstract: Synplify tmr Synplicity* haps encounter conformal equivalence check user guide Verilog code subtractor "module compiler" A3P400 implementing ALU with adder/subtractor CL169 MF138 Text: Synopsys FPGA Synthesis Synplify Pro Actel Edition User Guide October 2009 http://www.solvnet.com Disclaimer of Warranty Synopsys, Inc. makes no representations or warranties, either expressed or implied, by or with respect to anything in this manual, and shall not be liable	Original		PDF
Untitled Abstract: No abstract text available Text: Press Release CYPRESS SUPPORTS SYNOPSYS LOGIC MODELING SmartModels FOR ALL SPECIALTY MEMORIES Models Speed Design Time; Supported on Popular Simulation Platforms SAN JOSE, Calif., October 21, 1999Cypress Semiconductor Corporation NYSE:CY today announced that it has engaged in a partnership with Synopsys to support Logic Modeling SmartModels	Original	1999Cypress FlEx36	PDF
CLK48 Abstract: No abstract text available Text: Demonstration Screens Constraint Entry using Synopsys FPGA Express USB DEMO – 1 FPGA Express Supports Global Constaints 80 ns clock constraint applies to all flip-flops in this design USB DEMO – 2 Predefined Group Constraints Derived From Clock Default groups are	Original	CLK48 CLK48	PDF
simulation models Abstract: VME isa RC4640 RC4650 RC5000 RC64474 RC64475 synopsys memory Text: Simulation Tools/Models Synopsis, Inc. Logic Modeling Features Description ◆ Comprehensive approach to simulation modeling needs ◆ Broadest device coverage: microprocessor, FPGAs, PLDs, DSPs, logic and memories Synopsys' Logic Modeling products are the leading source of	Original		PDF
synopsys leda tool Abstract: hapstrak astro tools synopsys of counter project Text: Identify Actel Edition Quick Start Guide September 2009 http://solvnet.synopsys.com Disclaimer of Warranty Synopsys, Inc. makes no representations or warranties, either expressed or implied, by or with respect to anything in this manual, and shall not be liable	Original		PDF
"Constant fraction discriminator" Abstract: cti pet Constant fraction discriminator SIEMENS BST vhdl cordic code EPC1064V HP 30 pin lcd flex cable pinout vhdl code for cordic Constant fraction timing discriminator EPF10K50EQI240-2 Text: & News Views First Quarter, February 2000 The Programmable Solutions Company Newsletter for Altera Customers Altera Provides World-Class HDL Synthesis & Simulation Tools Altera has entered into agreements with Synopsys, Inc., and Mentor Graphics Corporation that enable Altera’s entire	Original		PDF
adc verilog Abstract: CS71 Text: CS71 Series Standard Cell ▼ 0.25µm CMOS Technology Features ▼ • 0.18µm Leff 0.24µm drawn • Up to 10 million gates • 0.05µW/gate/MHz power dissipation • 2.5V, 3.3V, 5V tolerant I/O options • Special high-performance I/Os–PCML, LVDS, PCI, SSTL, GTL+, AGP, USB	Original	ASIC-FS-20690-11/99 adc verilog CS71	PDF
JD 1804 Abstract: CS71 Text: CS71 Series Standard Cell t 0.25µm CMOS Technology Features t • 0.18µm Leff 0.24µm drawn • Up to 10 million gates • 0.05µW/gate/MHz power dissipation • 2.5V, 3.3V, 5V tolerant I/O options • Special high-performance I/Os–PCML, LVDS, PCI, SSTL, GTL+, AGP, USB	Original	ASIC-FS-20690-11/99 JD 1804 CS71	PDF
CS71 Abstract: No abstract text available Text: CS71 Series Standard Cell t 0.25µm CMOS Technology Features t • 0.18µm Leff 0.24µm drawn • Up to 10 million gates • 0.05µW/gate/MHz power dissipation • 2.5V, 3.3V, 5V tolerant I/O options • Special high-performance I/Os–PCML, LVDS, PCI, SSTL, GTL+, AGP, USB	Original	ASIC-FS-20690-11/99 CS71	PDF
verilog code for UART with BIST capability Abstract: VHDL CODE FOR HDLC controller ARM dual port SRAM compiler DesignWare SPI vhdl code for watchdog timer of ATM vhdl coding for analog to digital converter Sun Enterprise 250 static SRAM single-port verilog code for 16 bit risc processor verilog code arm processor Text: GS30 0.15-µm CMOS Standard Cell/Gate Array Version 0.2 May 16, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the	Original		PDF
NEC-V850 Abstract: DesignWare SPI vhdl code for watchdog timer of ATM ARM dual port SRAM compiler vhdl coding for analog to digital converter LogicVision verilog for SRAM 512k word 16bit uart verilog lvds synopsys on-chip modeling Text: GS30 0.15-µm CMOS Standard Cell/Gate Array Version 1.0 February, 2001 Copyright  Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the	Original	SRST145 NEC-V850 DesignWare SPI vhdl code for watchdog timer of ATM ARM dual port SRAM compiler vhdl coding for analog to digital converter LogicVision verilog for SRAM 512k word 16bit uart verilog lvds synopsys on-chip modeling	PDF

Netstat Commands Abstract: pendrive CRC32 usleep "routing tables" Text: UM0477 User Manual SPEAr Plus Linux SDK, embedded root filesystem Introduction This document provides information about the root filesystem for embedded applications provided with the SPEAr Plus Linux SDK, ver 1.1. The root filesystem provides the main Linux file structure accessible to user space, in	Original	UM0477 Netstat Commands pendrive CRC32 usleep "routing tables"	PDF
144 QFP body size Abstract: 35x35 bga BGA and QFP Package vhdl code for usart DesignWare SPI 0.18-um CMOS technology characteristics ARM7 verilog code NEC-V850 PZT driver design vhdl coding for analog to digital converter Text: GS20 0.18-µm CMOS Standard Cell/Gate Array Version 1.0 April 6, 1999 Copyright  Texas Instruments Incorporated, 1999 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the	Original		PDF
ARM dual port SRAM compiler Abstract: rm2510 synopsys dc ultra DSPG 16C450 16C550 ARM920T ARM940T IEEE1284 STD110 Text: V S MSUNG STD130 ELECTRONICS STD130 Standard Cell 0.18um System-On-Chip ASIC Dec 2000, V2.0 Features 1.8/2.5/3.3V - Leff= 0.15um, Ldrawn = 0.18um Device - Up to 23 million gates - Power dissipation :24nW/MHz 3.3/5.0V - Gate Delay : 48ps @ 1.8V, 1SL Device	Original	STD130 STD130 24nW/MHz ARM920T/ARM940T, ARM dual port SRAM compiler rm2510 synopsys dc ultra DSPG 16C450 16C550 ARM920T ARM940T IEEE1284 STD110	PDF
datasheet of BGA Staggered pins Abstract: NEC-V850 VHDL CODE FOR HDLC controller vhdl code for 4 channel dma controller clock tree balancing serdes transceiver 1999 verilog code for i2c vhdl code download for memory in cam vhdl code for watchdog timer of ATM vhdl coding for analog to digital converter Text: GS30 0.15-µm CMOS Standard Cell/Gate Array High-Value ASIC ❑ 0.15-µm Leff process 0.18-µm drawn with Shallow Trench Isolation (STI) Inline bond pads Minimum height I/Os Minimum width I/O ❑ 4 and 5 levels of metal ❑ 6 million random logic gates plus 6 million	Original		PDF
L9013Q13Q Abstract: MSM13Q floorplan io uart vhdl Text: MSM13Q0000/14Q0000 0.35 µm Sea of Gates Arrays DESCRIPTION Oki’s 0.3 5 µm ASIC products deliver ultra-high performance and high density at low power dissipation. The MSM13Q0000/14Q0000 series devices referred to as “MSM13Q/14Q” are implemented with the	Original	MSM13Q0000/14Q0000 MSM13Q0000/14Q0000 MSM13Q/14Q" MSM13Q) MSM14Q) 64-Mbit MSM13Q/14Q 1-800-OKI-6994 L9013Q13Q MSM13Q floorplan io uart vhdl	PDF
DSPG Abstract: Samsung Soc processor STD110 ASIC 16C450 16C550 ARM920T ARM940T IEEE1284 STD110 piler Text: V S MSUNG STD131 ELECTRONICS STD131 Standard Cell 0.18um System-On-Chip ASIC Dec 2000, V2.0 Features 1.8/2.5/3.3V - Leff= 0.15um, Ldrawn = 0.18um Device - Up to 23 million gates - Power dissipation :24nW/MHz 3.3/5.0V - Gate Delay : 48ps @ 1.8V, 1SL Device	Original	STD131 STD131 24nW/MHz ARM920T/ARM940T, DSPG Samsung Soc processor STD110 ASIC 16C450 16C550 ARM920T ARM940T IEEE1284 STD110 piler	PDF
ARM dual port SRAM compiler Abstract: designware i2c verilog code voltage regulator NEC-V850 ARM10 ARM946 TMS320C54X fastscan TI ASIC gs40 LogicVision Text: GS40 0.11-µm CMOS Standard Cell/Gate Array Version 1.0 January 29, 2001 Copyright  Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the	Original	SRST143 ARM dual port SRAM compiler designware i2c verilog code voltage regulator NEC-V850 ARM10 ARM946 TMS320C54X fastscan TI ASIC gs40 LogicVision	PDF
synopsys Platform Architect Abstract: clock tree balancing DesignWare SPI vhdl code for watchdog timer of ATM 0.18-um CMOS technology characteristics vhdl coding for analog to digital converter CML Vterm 27x27 Text: GS20 0.18-µm CMOS Standard Cell/Gate Array Version 1.1 May 19, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the	Original		PDF
verilog code voltage regulator Abstract: verilog code for 32 bit risc processor vhdl code for watchdog timer of ATM fastscan verilog code for 16 bit risc processor NET 1672 analog to digital converter verilog Multi-Channel DMA Controller verilog code arm processor Texas Instruments I2C Text: GS30TR 0.15-µm CMOS Standard Cell/Gate Array Version 1.2 May 17, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the	Original	GS30TR verilog code voltage regulator verilog code for 32 bit risc processor vhdl code for watchdog timer of ATM fastscan verilog code for 16 bit risc processor NET 1672 analog to digital converter verilog Multi-Channel DMA Controller verilog code arm processor Texas Instruments I2C	PDF
Untitled Abstract: No abstract text available Text: Oki Semiconductor MSM13Q/14Q 0.35 \|im Sea of Gates Arrays DESCRIPTION Oki's 0.3 5 Jim ASIC products deliver ultra-high performance and high density at low power dissipation. The M SM 13Q0000/14Q0000 series devices referred to as "M SM 13Q /14Q " are implemented with the	OCR Scan	MSM13Q/14Q 13Q0000/14Q0000 MSM13Q) MSM14Q) 64-Mbit 13Q/14Q 28x28 32x32	PDF

SYNOPSYS USB Search Results

SYNOPSYS USB Result Highlights (5)

SYNOPSYS USB Datasheets Context Search

16V8

16V8

Untitled

hapstrak

Untitled

CLK48

simulation models

synopsys leda tool

"Constant fraction discriminator"

adc verilog

JD 1804

CS71

verilog code for UART with BIST capability

NEC-V850

Netstat Commands

144 QFP body size

ARM dual port SRAM compiler

datasheet of BGA Staggered pins

L9013Q13Q

DSPG

ARM dual port SRAM compiler

synopsys Platform Architect

verilog code voltage regulator

Untitled