ZL50011QCG1
Abstract: GR-1244-CORE MS-026 ZL50011
Text: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features • March 2006 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation Ordering Information 160 Pin LQFP Trays 144 Ball LBGA Trays 160 Pin LQFP* Trays, Bake & Drypack
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ZL50011
ZL50011/QCC
ZL50011/GDC
ZL50011QCG1
ZL50011GDG2
GR-1244-CORE
ZL50011QCG1
MS-026
ZL50011
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ZL50010
Abstract: TFR1M GR-1244-CORE MS-026
Text: ZL50010 Flexible 512-ch DX with Enhanced DPLL Data Sheet Features VDD ZL50010/QCC ZL50010/GDC • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15
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PDF
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ZL50010
512-ch
STi0-15
ZL50010/QCC
ZL50010/GDC
IEEE-1149
ZL50010
TFR1M
GR-1244-CORE
MS-026
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GR-1244-CORE
Abstract: MS-026 ZL50011 11CH marking
Text: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features July 2004 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL
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PDF
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ZL50011
GR-1244-CORE
MS-026
ZL50011
11CH marking
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GR-1244-CORE
Abstract: MS-026 ZL50010
Text: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay
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Original
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PDF
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ZL50010
STi0-15
ZL50010/QCC
ZL50010/GDC
IEEE-1149
GR-1244-CORE
MS-026
ZL50010
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ZL50010QCG1
Abstract: GR-1244-CORE MS-026 ZL50010 32CH1
Text: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15 FPo0 CKo0
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Original
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PDF
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ZL50010
STi0-15
ZL50010/QCC
ZL50010/GDC
ZL50010QCG1
ZL50010GDG2
ZL50010QCG1
GR-1244-CORE
MS-026
ZL50010
32CH1
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GR-1244-CORE
Abstract: MS-026 ZL50010 TFPW0
Text: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay
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Original
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PDF
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ZL50010
STi0-15
ZL50010/QCC
ZL50010/GDC
IEEE-1149
GR-1244-CORE
MS-026
ZL50010
TFPW0
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Untitled
Abstract: No abstract text available
Text: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features July 2005 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL
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Original
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PDF
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ZL50011
GR-1244-CORE
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FOX 20.000 MHZ
Abstract: LMT 324 slv ca2 GR-1244-CORE MS-026 ZL50010 STO14 tfk8k
Text: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay
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Original
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PDF
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ZL50010
STi0-15
ZL50010/QCC
ZL50010/GDC
IEEE-1149
FOX 20.000 MHZ
LMT 324
slv ca2
GR-1244-CORE
MS-026
ZL50010
STO14
tfk8k
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GR-1244-CORE
Abstract: MS-026 ZL50011
Text: ZL50011 Flexible 512-ch DX with on-chip DPLL Data Sheet Features VDD • • • Applications • • • • • Small and medium digital switching platforms Access Servers Time Division Multiplexers Computer Telephony Integration Digital Loop Carriers VSS
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ZL50011
512-ch
STi0-15
GR-1244-CORE
MS-026
ZL50011
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tfk8k
Abstract: lg1001 LID17
Text: MT90866 WAN Access Switch Preliminary Information Features • • • • • • • • • • • • • • • • • • • • • • • • 3.3V operation with 5V tolerant inputs and I/O’s 5V tolerant PCI driver on CT-Bus I/O’s 2,432 x 2,432 non-blocking switching among local
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MT90866
192Mb/s
384Mb/s
048Mb/s,
096Mb/s
048Mb/s
tfk8k
lg1001
LID17
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32.768Mhz oscillator
Abstract: FOX 20.000 MHZ GR-1244-CORE MS-026 ZL50011 tfk8
Text: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features December 2003 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL
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Original
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PDF
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ZL50011
GR-1244-CORE
32.768Mhz oscillator
FOX 20.000 MHZ
MS-026
ZL50011
tfk8
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Untitled
Abstract: No abstract text available
Text: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features • September 2011 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation Ordering Information ZL50011/GDC 144 Ball LBGA Trays ZL50011QCG1 160 Pin LQFP* Trays, Bake & Drypack
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Original
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PDF
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ZL50011
ZL50011/GDC
ZL50011QCG1
ZL50011GDG2
GR-1244-CORE
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Untitled
Abstract: No abstract text available
Text: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD • • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15 FPo0 CKo0
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Original
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PDF
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ZL50010
STi0-15
ZL50010/GDC
ZL50010QCG1
ZL50010GDG2
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GR-1244-CORE
Abstract: MS-026 ZL50011
Text: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features December 2003 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL
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Original
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PDF
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ZL50011
GR-1244-CORE
MS-026
ZL50011
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