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    Infineon Technologies AG CY8C3665LTI-006

    IC MCU 8BIT 32KB FLASH 48QFN
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    DigiKey CY8C3665LTI-006 Tray 260
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    • 1000 $11.84112
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    Littelfuse Inc LA070URD30TTI0063

    FUSE SQUARE 63A 700VAC RECT
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey LA070URD30TTI0063 Box 1
    • 1 $218.78
    • 10 $218.78
    • 100 $218.78
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    Zakłady Kablowe BITNER TI0060

    Wire; BiTLAN,U/UTP; 4x2x24AWG; 5e; data transmission,outdoor
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    TME TI0060 1,000 5
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    • 10 $0.697
    • 100 $0.465
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    Zakłady Kablowe BITNER TI0066

    Wire; BiTLAN,F/UTP; 4x2x23AWG; 6; wire; Cu; polyethylene; black; 8mm
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    TME TI0066 5
    • 1 -
    • 10 $1.28
    • 100 $0.85
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    Adimpex srl KTI00630-RTP-1194R-58

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    Chip-Germany GmbH KTI00630-RTP-1194R-58 464
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    TI006 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Arcol wirewound resistor

    Abstract: TI002 Arcol HS50 NHS300 HS75 1K F hs50 100 1 TI005 TI006 HS300 ARCOL 19K36
    Text: HEATSINK RANGE TECHNICAL INFORMATION LAST REVISED 01 NOV 2001 CONTENTS Critical Resistance TI002 Critical Resistance TI005 Critical Voltage TI002 Definition of Terms TI005 Derating Curve HS TI007 Electromagnetic Compatibility (EMC) TI009 Heatsink Selection


    Original     		PDF TI002 TI005 TI007 TI009 TI001 TI003 TI006 Arcol wirewound resistor TI002 Arcol HS50 NHS300 HS75 1K F hs50 100 1 TI005 TI006 HS300 ARCOL 19K36

    Untitled

    Abstract: No abstract text available
    Text: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW


    OCR Scan     		PDF 54AC11109, 74AC11109 TI0066-- D2957, 500-mA STD-883C 300-mil 54AC11109 74AC11109

    Untitled

    Abstract: No abstract text available
    Text: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to


    OCR Scan     		PDF 54AC11032, 74AC11032 TI0060-- D2957, 500-mA 300-mil 54AC11032

    54ACT11034

    Abstract: 74ACT11034 D2957
    Text: 54ACT11034, 74ACT11034 HEX NONINVERTERS TI0063— D2957, FEBRU ARY 198ft— REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 54ACT11034 . . . J PACKAGE 74ACT11034 . . . DW OR N PACKAGE Flow-Through Architecture to Optimize PCB Layout o D1A 19 18 17


    OCR Scan     		PDF 54ACT11034, 74ACT11034 TI0063â D2957, 198ftâ 500-mA 300-mil 54ACT11034 74ACT11034 D2957

    U2-15

    Abstract: No abstract text available
    Text: 54ACT11074, 74ACT11074 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0065— D2957, DECEM BER 198«— R EVISED MARCH 1990 54ACT11074 . . . J PACKAGE 74 ACT 11074 . . . D O R N PACKAGE Inputs are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB


    OCR Scan     		PDF 54ACT11074, 74ACT11074 TI0065-- D2957, 500-mA 300-mil 54ACT11074 U2-15

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11238, 74ACT11238 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS TI0069— D3185, NOVEMBER 1988—REVISED MARCH 19 Inputs are TTL-Voltage Compatible 54ACT11238 . . . J PACKAGE 74ACT11238 . . . D OR N PACKAGE Designed Specifically for High-Speed Memory Decoders and Data Transmission


    OCR Scan     		PDF 54ACT11238, 74ACT11238 TI0069-- D3185, 1988--REVISED ACT11138 500-mA 300-mil 54ACT11238 T11238

    74ACT11074

    Abstract: D2957 1966-REVISED 54ACT11074
    Text: 54ACT11074, 74ACT11074 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0065— D2B57, DECEMBER 1986—REVISED MARCH 1990 Inputs are TTL-Voltage Compatible 54ACT11074 . . . J PACKAGE 74ACT11074 . . . D OR N PACKAGE Flow-Through Architecture to Optimize PCB


    OCR Scan     		PDF 54ACT11074, 74ACT11074 TI0065â D2B57, 500-mA 300-mil D2957 1966-REVISED 54ACT11074

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11034, 74ACT11034 HEX NONINVERTERS TI0063— D2957, FEBRUARY 1988— REVISED MARCH 1990 54ACT11034 . . . J PACKAGE 74ACT11034 . . . DW OR N PACKAGE • Inputs are TTL-Voltage Compatible • Flow-Through Architecture to Optimize PCB Layout TOP VIEW iv C 1 U 2 0 D ia


    OCR Scan     		PDF 54ACT11034, 74ACT11034 TI0063-- D2957, 500-mA 300-mil 54ACT11034 74ACT11034

    AC11074

    Abstract: 74AC 74AC11074 D2957 T10064-D2957
    Text: 54AC11074, 74AC11074 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0064— D2957, DECEMBER 1986— REVISED MARCH 1990 5 4A C 11 0 74 . . . J P A C K A G E 74A C 11074 . . . D O R N PACKAGE Flow-Through Architecture to Optimize PCB


    OCR Scan     		PDF 54AC11074, TI0064â D2957, 500-mA 300-mil AC11074 74AC 74AC11074 D2957 T10064-D2957

    54AC11034

    Abstract: 74AC11034 D2957
    Text: 54AC 11034, 74AC11034 HEX NONINVERTERS TI0062— D2957, FEBRUARY 1988— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54A C 11 0 34 . . . J P A C K A G E 7 4A C 11 0 34 . . . D W O R N P ACKA G E TO P V IE W Center-Pin V cc and GND Configurations to


    OCR Scan     		PDF 74AC11034 TI0062â D2957, 500-mA 300-mil 54AC11034 74AC11034 TI0062 D2957

    AC1123

    Abstract: UX11
    Text: 54AC11238, 74AC11238 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS TI0068— D3103, APRIL 1988—REVISEO JANUARY 1990 • Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems S 4A C 1 1238 . . . J P ACKA G E 7 4 A C 11 2 38 . . . D O R N P ACKA G E


    OCR Scan     		PDF 54AC11238, 74AC11238 TI0068-- D3103, 1988--REVISEO AC11138 500-mA 300-mil 32-BIT AC1123 UX11

    D3103

    Abstract: IEEE 1101.2 54AC11238 74AC 74AC11238 AC1123 AC11238
    Text: 54AC11238, 74AC11238 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS TI0068— D3103, APRIL 1988— R EVISED JANUARY 1990 54AC11238 . . . J PACKAGE 74AC11236 . . . D Oft N PACKAGE Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems


    OCR Scan     		PDF 54AC11238, TI0068â D3103, AC11138 500-mA 300-mil AC11238 ac11238 D3103 IEEE 1101.2 54AC11238 74AC 74AC11238 AC1123

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0067— D2957, FEBRUARY 1987— REVISED JANUARY 1990 • Inputs are TTL-Voltage Compatible 54AC T11109 . . . J PAC KAG E 74A C T11109 . . . D OR N PAC KAG E • Flow-Through Architecture to Optimize PCB


    OCR Scan     		PDF 54ACT11109, 74ACT11109 TI0067-- D2957, 500-mA 300-mil

    AC11074

    Abstract: No abstract text available
    Text: 54AC11074, 74AC11074 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0064—02957, DECEMBER 1986—REVISED MARCH 1990 • Flow-Through Architecture to Optimize PCB Layout 54AC11074 . . . J PACKAGE 74AC11074 . . . O OR N PACKAGE TOP VIEW


    OCR Scan     		PDF 54AC11074, 74AC11074 TI0064--02957, 1986--REVISED 500-mA 300-mil AC11074

    54ACT11109

    Abstract: 74ACT11109 D2957 611H
    Text: _ 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET T I0 0 6 7 — D 2 9 5 7 , F E B R U A R Y 1 9 8 7 — R E V I S E D J A N U A R Y 1 9 9 0 Inputs are TTL-Voltage Compatible 54ACT11109 . . . J P A C K A G E 74ACT11109 . . D O R N P A C K A G E


    OCR Scan     		PDF 54ACT11109, 74ACT11109 TI0067â D2957, 500-mA 300-mil 54ACT11109 D2957 611H

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11032, 74ACT11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES T10061— D2957, JULY 1987—REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 5 4 A C T 11 0 32 . . . J P ACKA G E 7 4 A C T 11 0 32 . . . O OR N P ACKA G E • Flow-Through Architecture to Optimize PCB


    OCR Scan     		PDF 54ACT11032, 74ACT11032 T10061-- D2957, 1987--REVISED 500-mA 300-mil

    D2967

    Abstract: 74ACT11032 D2957 364Bh 54ACT11032
    Text: 54ACT11032, 74ACT11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TP0061 —D2957, JULY 19B7—REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 54ACT11032 . . . J PACKAGE 74ACT11032 . . . D O R I 4 PACKAGE Flow-Through Architecture to Optimize PCB Layout


    OCR Scan     		PDF 54ACT11032, 74ACT11032 TP0061â D2957, 500-mA 300-mil 54ACT11032 D2967 74ACT11032 D2957 364Bh

    Untitled

    Abstract: No abstract text available
    Text: 54AC 11020, 74AC11020 DUAL 4-INPUT POSITIVE-NAND GATES TI0052— D2957, MARCH 1987— REVISED MARCH 1990 S4AC11020 . . . J PACKAGE 74AC11020 . . . D OR N PACKAGE Flow-Through Architecture to Optimize PCB Layout TOP VIEW Center-Pin V c c and GND Configurations to


    OCR Scan     		PDF 74AC11020 TI0052-- D2957, 500-mA 300-mll S4AC11020 74AC11020 54AC11020 I0052-- D2957.

    54ACT11521

    Abstract: 74ACT11521 D2957 TI0084
    Text: 54ACT11521, 74ACT11521 8-BIT IDENTITY COMPARATORS TI0084— D2957, JULY 1987— R EVISED MARCH 1990 54ACT11521 . . . J PACKAGE 74ACT11521 . . . DW OR N PACKAGE Inputs are TTL-Voltage Compatible Compares Two 8-Bit Words TOP VIEW Flow-Through Architecture to Optimize PCB


    OCR Scan     		PDF 54ACT11521, 74ACT TI0084â D2957, 500-mA 300-mil 54ACT11521 74ACT11521 D2957 TI0084

    54AC11109

    Abstract: 74AC11109 D2957
    Text: _ 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET T I0 0 6 6 — D 2 9 5 7 , M A R C H 1 9 8 7 — R E V IS E D M A R C H 1 9 9 0 54A C 11109 I PACKAGE 7 4 A C 1 1109 . . . D O R N P A C K A G E Flow-Through Architecture to Optimize PCB


    OCR Scan     		PDF 54AC11109, 74AC11109 TI0066â D2957, 500-mA STD-883C 300-mil 54AC11109 D2957

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11533, 74ACT11533 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS TIOO06— D2957, JULY 1987—REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 54AC T11533 . . . JT PAC KAG E 7 4 A C T 1 1 5 3 3 . . . D W OR N T P A C K A G E • 8-Latches In a Single Package


    OCR Scan     		PDF 54ACT11533, 74ACT11533 TIOO06-- D2957, 1987--REVISED 500-mA 300-mil T11533

    Untitled

    Abstract: No abstract text available
    Text: 54AC11034, 74AC11034 HEX NONINVERTERS T I0062— D2957, FEBRUARY 1988— REVISED MARCH 1990 • Flow-Through Architecture to Optimize PCB Layout 5 4 A C 11 0 34 . . . J P ACKA G E 7 4 A C 1 1034 . . . D W O R N P ACKA G E TO P V IE W • Center-PIn Vcc and GND Configurations to


    OCR Scan     		PDF 54AC11034, 74AC11034 I0062-- D2957, 500-mA 300-mll D2857, TI0062

    D3185

    Abstract: No abstract text available
    Text: 31E D TEXAS INSTR LOGIC 6*^1723 DOflaTeS b • T I I 3 54ACT11238, 74ACT11238 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS Ce l - Z J - 5 5 908— T10069— D3185, NOVEMBER 198 9 -RREVISEb E V ISE b'MhA R C H 1990 54ACT11238 . . . J P A C K A G E 74ACT11238 . . D O R N P A C K A G E


    OCR Scan     		PDF 54ACT11238, 74ACT11238 T10069â D3185, 54ACT11238 ACT11138 24-BIT 74ACT11238 D3185

    TIG060-D2957

    Abstract: AC11032 74AC 74AC11032 D2957
    Text: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TIG060— D2957, JULY 1987— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54A C 11032 I PACKAGE 74AC11032 . . . D OR N PACKAGE TOP VIEW Center-Pin Vcc and GND Configurations to


    OCR Scan     		PDF 54AC11032, TIG060â D2957, 500-mA 300-mil 54AC11032 74AC11032 TI0060â TIG060-D2957 AC11032 74AC D2957