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    VIRTEX ANALOG TO DIGITAL CONVERTER Search Results

    VIRTEX ANALOG TO DIGITAL CONVERTER Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    DCL541A01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: Low / Input disable Visit Toshiba Electronic Devices & Storage Corporation
    DCL542H01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=2:2) / Default Output Logic: High / Output enable Visit Toshiba Electronic Devices & Storage Corporation
    DCL541B01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: High / Input disable Visit Toshiba Electronic Devices & Storage Corporation
    DCL542L01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=2:2) / Default Output Logic: Low / Output enable Visit Toshiba Electronic Devices & Storage Corporation
    DCL540H01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=4:0) / Default Output Logic: High / Output enable Visit Toshiba Electronic Devices & Storage Corporation

    VIRTEX ANALOG TO DIGITAL CONVERTER Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    XAPP873

    Abstract: OSERDES VHDL description for an 8-bit even/odd parity MB86065 IOL13 RAM64X1D RAMB36 Virtex-5 write operation using ram in fpga ML550
    Text: Application Note: Virtex-5 FPGAs R XAPP873 v1.0 May 6, 2008 Virtex-5 FPGA Interface for Fujitsu Digital-to-Analog Converters with LVDS Inputs Author: Marc Defossez Summary This application note describes how to interface a Fujitsu MB86064 digital-to-analog


    Original     		PDF XAPP873 MB86064 MB86065 XAPP873 OSERDES VHDL description for an 8-bit even/odd parity IOL13 RAM64X1D RAMB36 Virtex-5 write operation using ram in fpga ML550

    OSERDES

    Abstract: DAC FPGA START KIT Virtex-5 FPGA Packaging and Pinout Specification XAPP873 pcb layout design mobile DDR parallel to serial conversion vhdl RAMB36 iodelay fpga cdma ip vhdl examples ML550
    Text: Application Note: Virtex-5 FPGAs R XAPP873 v1.2 June 15, 2010 Virtex-5 FPGA Interface for Fujitsu Digital-to-Analog Converters with LVDS Inputs Author: Marc Defossez Summary This application note describes how to interface a Fujitsu MB86064 digital-to-analog


    Original     		PDF XAPP873 MB86064 MB86065 OSERDES DAC FPGA START KIT Virtex-5 FPGA Packaging and Pinout Specification XAPP873 pcb layout design mobile DDR parallel to serial conversion vhdl RAMB36 iodelay fpga cdma ip vhdl examples ML550

    OSERDES

    Abstract: RAMB36 ML555 MB86064 MB86065 ML550 XAPP873 RAM64X1D iodelay vhdl code for DCM
    Text: Application Note: Virtex-5 FPGAs Virtex-5 FPGA Interface for Fujitsu Digital-to-Analog Converters with LVDS Inputs R XAPP873 v1.1 December 7, 2009 Author: Marc Defossez Summary This application note describes how to interface a Fujitsu MB86064 digital-to-analog


    Original     		PDF XAPP873 MB86064 MB86065 OSERDES RAMB36 ML555 ML550 XAPP873 RAM64X1D iodelay vhdl code for DCM

    12-bit ADC interface vhdl code for FPGA

    Abstract: iodelay ISERDES XC5VLX50T-FF1136.xls VHDL code for high speed ADCs using SPI with FPGA 12-bit ADC interface vhdl complete code for FPGA virtex 4 date code for ADC XAPP866 iodelay for adc parallel data and fpga interface UCF virtex-4
    Text: Application Note: Virtex-4 and Virtex-5 FPGAs R XAPP866 v3.0 April 7, 2008 An Interface for Texas Instruments Analog-to-Digital Converters with Serial LVDS Outputs Author: Marc Defossez Summary This application note describes how to interface a Texas Instruments analog-to-digital


    Original     		PDF XAPP866 12-bit ADC interface vhdl code for FPGA iodelay ISERDES XC5VLX50T-FF1136.xls VHDL code for high speed ADCs using SPI with FPGA 12-bit ADC interface vhdl complete code for FPGA virtex 4 date code for ADC XAPP866 iodelay for adc parallel data and fpga interface UCF virtex-4

    VHDL code for ADC and DAC SPI with FPGA spartan 3

    Abstract: VHDL code for ADC and DAC SPI with FPGA 12-bit ADC interface vhdl code for FPGA direct sequence spread spectrum virtex JESD204 XAPP876 Xilinx ml507 prbs jesd VHDL code for high speed ADCs using SPI with FPGA virtex 4 date code for ADC
    Text: Application Note: Virtex-5 Family Virtex-5 FPGA Interface to a JESD204A Compliant ADC XAPP876 v1.0.1 February 22, 2010 Author: Marc Defossez Summary This application note describes how to interface the Virtex -5 LXT, SXT, TXT, and FXT devices featuring GTP/GTX transceivers to an analog-to-digital (ADC) converter compliant to JEDEC


    Original     		PDF JESD204A XAPP876 JESD204A) JESD204 JESD204A VHDL code for ADC and DAC SPI with FPGA spartan 3 VHDL code for ADC and DAC SPI with FPGA 12-bit ADC interface vhdl code for FPGA direct sequence spread spectrum virtex XAPP876 Xilinx ml507 prbs jesd VHDL code for high speed ADCs using SPI with FPGA virtex 4 date code for ADC

    VHDL code for ADC and DAC SPI with FPGA

    Abstract: VHDL code for ADC and DAC SPI with FPGA spartan 3 XAPP876 vhdl code for parallel to serial converter 12-bit ADC interface vhdl code for FPGA picoblaze UG347 DS202 JESD204 JESD204A
    Text: Application Note: Virtex-5 Family Virtex-5 FPGA Interface to a JESD204A Compliant ADC XAPP876 v1.0 September 18, 2009 Author: Marc Defossez Summary This application note describes how to interface the Virtex -5 LXT, SXT, TXT, and FXT devices featuring GTP/GTX transceivers to an analog-to-digital (ADC) converter compliant to JEDEC


    Original     		PDF JESD204A XAPP876 JESD204A) JESD204 JESD204A VHDL code for ADC and DAC SPI with FPGA VHDL code for ADC and DAC SPI with FPGA spartan 3 XAPP876 vhdl code for parallel to serial converter 12-bit ADC interface vhdl code for FPGA picoblaze UG347 DS202

    Untitled

    Abstract: No abstract text available
    Text: Ultra High-Speed Acquisition Board – Real Time Signal Processing General The UHAB Ultra High-speed Acquisition Board has both analog to digital and digital to analog converters on board as well as two Virtex-4 SX35 FPGAs, one for DSP and the other for data


    Original     		PDF 14bit 100x160 RS232) 2Mx32 4Mx32 8Mx32) 167MHz AD9736 2/4/8Mx32 RJ-45

    verilog code for adc

    Abstract: verilog code of 8 bit comparator ADC Verilog Implementation ADC DAC Verilog 2 bit Implementation verilog code of 16 bit comparator adc verilog analog to digital converter verilog verilog code of 4 bit comparator verilog code of 3 bit comparator verilog code for serial multiplier
    Text: APPLICATION NOTE APPLICATION NOTE 5  XAPP155 September 23, 1999 Version 1.1 Virtex Analog to Digital Converter 13* Application Note: John Logue Summary When digital systems are used in real-world applications, it is often necessary to convert an analog voltage level to a binary number. The value of this


    Original     		PDF XAPP155 10-bit CLK90( CLK180( CLK270( verilog code for adc verilog code of 8 bit comparator ADC Verilog Implementation ADC DAC Verilog 2 bit Implementation verilog code of 16 bit comparator adc verilog analog to digital converter verilog verilog code of 4 bit comparator verilog code of 3 bit comparator verilog code for serial multiplier

    resistor network

    Abstract: network resistor integrated AN1165 APP1165 MAX5195 Virtex Analog to Digital Converter
    Text: Maxim > App Notes > A/D and D/A CONVERSION/SAMPLING CIRCUITS BASESTATIONS / WIRELESS INFRASTRUCTURE HIGH-SPEED SIGNAL PROCESSING Keywords: high speed DAC, digital to analog converter, DACs, LVPECL input levels, FPGA, Xilinx, Virtex, interface, Altera, Apex


    Original     		PDF MAX5195 14-bit, 260Msps com/an1165 MAX5195: AN1165, APP1165, resistor network network resistor integrated AN1165 APP1165 Virtex Analog to Digital Converter

    XAPP154

    Abstract: ADC DAC Verilog 2 bit Implementation binary pulse dac XAPP130 XAPP155 schematic diagram dac XAPP132 XAPP133 Virtex Analog to Digital Converter ADC Verilog Implementation
    Text: APPLICATION NOTE APPLICATION NOTE  Virtex Synthesizable Delta-Sigma DAC XAPP154 September 23, 1999 Version 1.1 13* Application Note by John Logue Summary Digital to analog converters (DACs) convert a binary number into a voltage directly proportional to the value of the binary number. A variety of


    Original     		PDF XAPP154 10-bit ADC DAC Verilog 2 bit Implementation binary pulse dac XAPP130 XAPP155 schematic diagram dac XAPP132 XAPP133 Virtex Analog to Digital Converter ADC Verilog Implementation

    Untitled

    Abstract: No abstract text available
    Text: Best-in-Class ADCs & DACs Best-in-Class ADCs & DACs – IDT High-Speed ADC/DAC Selection Guide Integrated DeviceTechnology | | POWER MANAGEMENT ANALOG & RF INTERFACE & CONNECTIVITY | CLOCKS & TIMING | MEMORY & LOGIC | TOUCH & USER INTERFACE | DATA CONVERTER


    Original     		PDF DAC1001D125 DAC1001D125-DB DAC1001D125 DAC1003D160 DAC1003D160-DB DAC1003D160 DAC1005D650-DB DAC1005D650 DAC1005D750-DB DAC1005D750

    VHDL code for dac

    Abstract: vhdl code for spartan 6 audio XAPP154 DS487 12 bit DAC VHDL CODE XAPP130 XAPP155 IPIF DAC spartan 3 XAPP133
    Text: OPB Delta-Sigma DAC v1.01a DS487 December 1, 2005 Product Specification Introduction LogiCORE Facts Digital to analog converters (DACs) convert a binary number into a voltage directly proportional to the value of the binary number. A variety of applications use


    Original     		PDF DS487 XAPP154 VHDL code for dac vhdl code for spartan 6 audio 12 bit DAC VHDL CODE XAPP130 XAPP155 IPIF DAC spartan 3 XAPP133

    cpld 95108

    Abstract: XCV200-6PQ240C XCV1000E-6HQ240C XCV800-6HQ240C XCV100E-6PQ240C XCV200E-6PQ240C XCV300E-6PQ240C XCV400E-6HQ240C XCV50-6PQ240C XCV50E-6PQ240C
    Text: GVA-270 Virtex -E DSP Hardware Accelerator Revision A April 3, 2000 GV & Associates, Inc. 23540 Oriente Way Ramona, CA 92065 USA Phone: +1 760-789-7015 Fax: +1 760-789-7015 E-mail: [email protected] Web: www.gvassociates.com Features • • • •


    Original     		PDF GVA-270 40-bit 65MHz 12-Bit AD6640) AD9762) XCV1000E6HQ240C 120MSPS cpld 95108 XCV200-6PQ240C XCV1000E-6HQ240C XCV800-6HQ240C XCV100E-6PQ240C XCV200E-6PQ240C XCV300E-6PQ240C XCV400E-6HQ240C XCV50-6PQ240C XCV50E-6PQ240C

    free circuit diagram of motherboard

    Abstract: Data Conversion XCV3200E XCV400 Digital Converters Virtex
    Text: Success Story - A/D Conversion Module Simultaneous 4-channel, 12-bit A/D Conversion Using Virtex FPGAs you can now process 600 Mbytes/s of data, a previously impossible task even with today’s state-of-the-art DSP Processors. by Neil Harold, Design Engineer, Nallatech Ltd,


    Original     		PDF 12-bit XCV400 XCV3200E 12-bit, free circuit diagram of motherboard Data Conversion Digital Converters Virtex

    Untitled

    Abstract: No abstract text available
    Text: The JESD204A interface – The key to broadband wireless system miniaturization December 2010 Bradley Loisel, Maury Wood - NXP Semiconductors Harpinder Matharu - Xilinx Corporation 0.0 Introduction - New and transformative high-speed data converter interface


    Original     		PDF JESD204A org/standards-documents/results/JESD204A.

    LM3874-Adj

    Abstract: LM3671 operational amplifier discrete schematic SCANSTA111 LP2985 LM2671 lm3485 LP3874-ADJ LM3874 SPARTAN-3 XC3S400
    Text: Analog Design Guide for Xilinx FPGAs Power Expert . 2 Power Management Solution for FPGAs . 3-19 High-Speed Interface Solution for FPGAs . 20-21 JTAG for FPGAs . 22-23 High-speed ADCs for FPGAs . 24-25


    Original     		PDF O-220 O-263 OT-23 LM3874-Adj LM3671 operational amplifier discrete schematic SCANSTA111 LP2985 LM2671 lm3485 LP3874-ADJ LM3874 SPARTAN-3 XC3S400

    4 bit binary multiplier Vhdl code

    Abstract: low pass Filter VHDL code vhdl code of 8 bit comparator VHDL code for dac vhdl code for serial analog to digital converter xilinx vhdl code for digital clock adc controller vhdl code IPIF vhdl code for digital to analog converter Xilinx analog comparator
    Text: DS OPB Delta-Sigma Analog to Digital Converter ADC (v1.01a) DS488 December 1, 2005 Product Specification Introduction LogiCORE Facts When digital systems are used in real-world applications, it is often necessary to convert an analog voltage level to a


    Original     		PDF DS488 Virtex-402 4 bit binary multiplier Vhdl code low pass Filter VHDL code vhdl code of 8 bit comparator VHDL code for dac vhdl code for serial analog to digital converter xilinx vhdl code for digital clock adc controller vhdl code IPIF vhdl code for digital to analog converter Xilinx analog comparator

    XAPP029

    Abstract: adc controller vhdl code verilog rtl code of Crossbar Switch 12-bit ADC interface vhdl code for FPGA vhdl code for pn sequence generator Insight Spartan-II demo board XAPP172 xilinx XC3000 SEU testing verilog hdl code for triple modular redundancy parallel to serial conversion vhdl IEEE paper
    Text: DataSource CD-ROM Q4-01 Xilinx Application Note Summaries XAPP004 Loadable Binary Counters The design strategies for loadable and non-loadable binary counters are significantly different. This application note discusses the differences, and describes the design of a loadable binary counter.


    Original     		PDF Q4-01 XAPP004 XAPP005 XC3000 Desi49 XC18V00, XC9500XL, XC9500XV, XAPP501 XC9500, XAPP029 adc controller vhdl code verilog rtl code of Crossbar Switch 12-bit ADC interface vhdl code for FPGA vhdl code for pn sequence generator Insight Spartan-II demo board XAPP172 xilinx XC3000 SEU testing verilog hdl code for triple modular redundancy parallel to serial conversion vhdl IEEE paper

    MB86064

    Abstract: Hitec MB86065 MB860 hitech Xilinx Ethernet development XC5VFX
    Text: The Fujitsu DKXC5VADAPT-1 Digital to Analog Converter DK FPGA Adaptor Adaptor Front Adaptor Back Complete System Description The DKXC5VADAPT-1 DAC DK adaptor provides a quick and effective way to demonstrate a high-speed data interface to the Fujitsu DK86064 and DK86065 high-performance


    Original     		PDF DK86064 DK86065 DK86064/65-2 EPS-FS-21355-11/2009 MB86064 Hitec MB86065 MB860 hitech Xilinx Ethernet development XC5VFX

    HVQFN64

    Abstract: HVQFN40 ADC1410S ADC1215S ADC1215S065 ADC1215S080 ADC1215S105 ADC1215S125 ADC1410S065 ADC1410S080
    Text: Type Related demoboard Description ADC1215S series ADC1215S065/DB ADC1215S065 demo board; both CMOS and LVDS ADC1215S080/DB ADC1215S080 demo board; both CMOS and LVDS ADC1215S105/DB ADC1215S105 demo board; both CMOS and LVDS ADC1215S125/DB ADC1215S125 demo board; both CMOS and LVDS


    Original     		PDF ADC1215S ADC1215S065/DB ADC1215S065 ADC1215S080/DB ADC1215S080 ADC1215S105/DB ADC1215S105 ADC1215S125/DB ADC1215S125 ADC1410S065/DB HVQFN64 HVQFN40 ADC1410S ADC1410S065 ADC1410S080

    convertisseur dc dc

    Abstract: DAC1408D 16888 LTE baseband convertisseur DAC1408D750 JESD204A nxp 32 bit Dual-channel Transceiver mimo frequency synthesizer for LTE Applications
    Text: NXP dual-channel 10, 12, 14 bits, up to 750 Msps D/A converter DAC1408D series JESD204A-compliant D/A conversion for wideband communication & instrumentation Optimized for high-speed applications, such as 2.5/3/4G wireless, video broadcast, and instrumentation, this advanced DAC has selectable interpolating filters and a four-lane CGV


    Original     		PDF DAC1408D JESD204A-compliant JESD204A. JESD204A HVQFN64 14-bit) convertisseur dc dc 16888 LTE baseband convertisseur DAC1408D750 nxp 32 bit Dual-channel Transceiver mimo frequency synthesizer for LTE Applications

    FLUXGATE

    Abstract: compass ic Fluxgate Magnetic Field Sensor fluxgate magnetometer anderton
    Text: Volume 5, Number 1 Winter 2000 A P u b l i c a t i o n o f A m e r i c a n M i c r o s y s t e m s , I n c . AMI develops DLL megacell for smooth translations of Xilinx Virtex FPGAs to ASICs By Bob Kirk Improving on the original cations that monitor subsystems


    Original     		PDF

    samtec connector

    Abstract: ADC0808D250 ADC0808D ADC1415S080 LVDS connector ADC1010S080 HVQFN64 DEMO
    Text: Type Related demoboard Description ADC1207S080 ADC1207S080/DB ADC1207S080 demo board ADC1210S series ADC1210S065/DB ADC1210S065 demo board; both CMOS and LVDS ADC1210S065F1/DB ADC1210S065 demo board; CMOS version; SPI, Regulators and CMOS buffer on board ADC1210S065F2/DB


    Original     		PDF ADC1207S080 ADC1207S080/DB ADC1207S080 ADC1210S ADC1210S065/DB ADC1210S065 ADC1210S065F1/DB ADC1210S065F2/DB ADC1413D125 samtec connector ADC0808D250 ADC0808D ADC1415S080 LVDS connector ADC1010S080 HVQFN64 DEMO

    matched filter in vhdl

    Abstract: XAPP012 Insight Spartan-II demo board vhdl code for crossbar switch XAPP029 verilog code for cdma transmitter FPGA Virtex 6 pin configuration xapp005 verilog code for 16 kb ram verilog code for crossbar switch
    Text: DataSource CD-ROM Q4-01 Xilinx Application Notes Summaries Title Size Summary Family Design Loadable Binary Counters 40 KB XAPP004 XC3000 VIEWlogi OrCAD Register Based FIFO 60 KB XAPP005 XC3000 VIEWlogi OrCAD Boundary Scan Emulator for XC3000 80 KB XAPP007 XC3000


    Original     		PDF Q4-01 XC3000 XC4000E XC4000 XC4000/XC5200 matched filter in vhdl XAPP012 Insight Spartan-II demo board vhdl code for crossbar switch XAPP029 verilog code for cdma transmitter FPGA Virtex 6 pin configuration xapp005 verilog code for 16 kb ram verilog code for crossbar switch