Untitled
Abstract: No abstract text available
Text: TLVH431A-Q1 TLVH431B-Q1 SLVS906B – DECEMBER 2008 – REVISED MARCH 2011 www.ti.com LOW-VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS Check for Samples: TLVH431A-Q1, TLVH431B-Q1 FEATURES 1 • • • Qualified for Automotive Applications Low-Voltage Operation: Down to 1.24 V
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TLVH431A-Q1
TLVH431B-Q1
SLVS906B
TLVH431A-Q1,
TLVH431
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DTA 2030
Abstract: No abstract text available
Text: TLVH431A-Q1 TLVH431B-Q1 SLVS906B – DECEMBER 2008 – REVISED MARCH 2011 www.ti.com LOW-VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS Check for Samples: TLVH431A-Q1, TLVH431B-Q1 FEATURES 1 • • • Qualified for Automotive Applications Low-Voltage Operation: Down to 1.24 V
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TLVH431A-Q1
TLVH431B-Q1
SLVS906B
TLVH431A-Q1,
TLVH431
DTA 2030
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67s18258
Abstract: No abstract text available
Text: for spcc. confirrnation SUN HM67S18258 Series 262144 words x 18 bits Synchronous Fast Static R A M P ro d u c t P review Rev. 3 HITACHI Features Dec. 10 1996 Pin A rrangem ent 3,3 V ± 5 % Operation LV C M O S C om patible Input and Output 1 2 ro O o OOo
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HM67S18258
HM57S18258ESP-6
67S18258BP-7
127mm
BP-119F)
67S18258BP-7H
PMMSCTD011
67s18258
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BP-119
Abstract: No abstract text available
Text: HM67S36130 Series 131,072-words x 36-bits Synchronous Fast Static RAM HITACHI ADE-203-659A Z Product Preview Rev. 1 Feb. 21, 1997 Features • 3.3V ± 5% Operation • LVCMOS Compatible Input and Output • Synchronous Operation • Internal self-timed Late Write
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HM67S36130
072-words
36-bits
ADE-203-659A
HM67S36130BP-7
BP-119)
HM67S18258BP-7H
HM67S18258BP-7
BP-119
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9436a
Abstract: No abstract text available
Text: ADVANCE MT55L128L18P, MT55L64L32P, MT55L64L36P 2.25Mb ZBT SRAM 3 .3V V od, Selectable Burst Mode FEATURES • • • • • • • • • • • • • • • • • High frequency and 100 percent bus utilization Fast cycle times: 7ns, 7.5ns, 8.5ns and 10ns
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12BKx
MT55L128L18P
9436a
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1P 2F MARKING
Abstract: No abstract text available
Text: ADVANCE |v i i c 2 5 6 K x 1 8 /1 2 8 K x 36 3 . 3 V Vod, HSTL. PIPELINED C L A Y M O R E SRAM :r o n R M h tt. U I V I U M T57L256H 18P M T57L128H 36P d FEATURES • • • • • • • • • • • • • • • • • • • • • Fast cycle times: 4.4ns, 5ns, 5.5ns, 6ns and 7ns
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T57L256H
T57L128H
18/126K
MT57L256H18P
C1996,
1P 2F MARKING
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82430TX
Abstract: CY2278A CPU-63 3D16E Jittek
Text: Pentium /!! Clock Synthesizer/Driver for Mobile PCs with Intel 82430TX and No SDRAM Features • Mixed 2.5V and 3.3V operation • Complete clock solution to meet requirements of mo bile Pentium® and Pentium® II motherboards — Seven CPU clock outputs three at 3.3V, and four at
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CY2278Ae
82430TX
CY2278A
CPU-63
3D16E
Jittek
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KM4132G271B
Abstract: No abstract text available
Text: KM4132G271B CMOS SGRAM 128K X 32Bit X 2 Banks Synchronous Graphic RAM FEATURES GENERAL DESCRIPTION • • • • The KM4132G271B is 8,388,608 bits synchronous high data rate Dynamic RAM organized as 2 x 131,072 words by 32 bits, fabricated with SAMSUNG'S high performance CMOS technol
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KM4132G271B
32Bit
KM4132G271B
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WKX 54
Abstract: WKX 62 WKX vll
Text: KM732V688/L 64Kx32 Synchronous SRAM 64Kx32-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • • • • • • • • • • • • • • The KM732V688/L is a 2,097,152 bit Synchronous Static Ran dom Access Memory designed for high performance second
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KM732V688/L
64Kx32
KM732V688/L
WKX 54
WKX 62
WKX vll
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Untitled
Abstract: No abstract text available
Text: KM736V695/L 64Kx36 Synchronous SRAM 64Kx36~Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • • • • • • • • • • • The KM736V695/L is a 2,359,296-bit Synchronous Static Ran dom Access Memory designed for high performance second
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KM736V695/L
64Kx36
KM736V695/L
296-bit
36bits
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6n7p
Abstract: SAL3
Text: KM736FV4011 KM718FV4011 PRELIMINARY 128KX36 & 256Kx18 SRAM 128Kx36 & 256Kx18 Synchronous Pipelined SRAM FEATURES • 128KX36 or 256Kx18 Organizations. • 3.3V Core/1,5V Output Power Supply. • HSTl Input and Output Levels. • Differential, HSTL Clock Inputs K, R.
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KM736FV4011
KM718FV4011
128KX36
256Kx18
128KX36
14mmx22mm)
KM736FV4011H-44
6n7p
SAL3
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Untitled
Abstract: No abstract text available
Text: KM718V895 256Kx18 Synchronous SRAM 256Kx18-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • 2 Stage Pipelined Operation With 4 Buret • On-Chip Address Counter. • Self-Timed Write Cyde. • On-Chip Address and Control Registers.
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KM718V895
100-TQFP-1420A
256Kx18
25SKx1S
256KX18
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Untitled
Abstract: No abstract text available
Text: IBM043611 ULAB IBM041811 ULAB Prelim inary 32K x 36 & 64K x 18 SRAM Features • 32K x 36 or 64K x 18 organizations • Registered outputs • 0.45 Micron CMOS technology • Asynchronous Output Enable and Power Down Inputs • Synchronous pipeline mode of operation with
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IBM043611
IBM041811
GA14-4669-02
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ci 8602 gn
Abstract: ci 8602 gn block diagram 12v dc cdi schematic diagram L146 IC 8602 gn Alc201A 12v dc cdi schematic diagram for cdi tk 1838 ir m6502 IR TK 1838
Text: Schematic Diagrams System Block Diagram M400 System Block Diagram Sheet 1 of 41 System Block Diagram Schematic Diagrams Socket 478 1 of 2 <O>HD#[0 *3] VCC CORK COin r- cr> ;-v^ s> ^ ^ :>;> r - ^ > > s> ^ s> ^ S ’- ^ ^ !•> ^ ^ N ^ ^ ^ ^ ^ ^ ^ ^ ^ r » : >
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C237D87N
STS-05-A
71-M4000-D03)
10MIL
STS-05-A
ci 8602 gn
ci 8602 gn block diagram
12v dc cdi schematic diagram
L146 IC
8602 gn
Alc201A
12v dc cdi schematic diagram for cdi
tk 1838 ir
m6502
IR TK 1838
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TC227
Abstract: IR sensor LFN 2N700Z S14800 U53D LS 2027 audio amp a-b osai em 231 rtd aa2c SOT23-5 LM2729
Text: Model: R15B R:0 Intel Banias+855PM+ICH4 PCB STACK UP LAY1 TOP LAY2 GND LAY3 IN1 LAY4 IN2 LAYS GND1 LAY6 VCC LAY7 IN3 LAY8 IN4 LAY9 GND2 LAY10 BOTTOM Revision History A Page Page Page Page Page Page Page Page Page Page Page ORIGINAL RELEASE 1 2 3 4 5 6 7 8
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855PM
LAY10
LM27281
LP2996
1AX1737
LM2729
SI4800
TC227
IR sensor LFN
2N700Z
S14800
U53D
LS 2027 audio amp
a-b osai
em 231 rtd
aa2c SOT23-5
LM2729
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Untitled
Abstract: No abstract text available
Text: I = = — = -= P relim inary IBM043610TLAA IBM04181OTLAA 3 2 K X 36 & 6 4 K X 1 8 S R A M Features • 32 K x 3 6 or 64K x 18 O rganizations • 0 .4 5 Micron C M O S Technology • Synchronous Flow -Thru M ode O f Operation with S elt-Tim ed Late W rite
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IBM043610TLAA
IBM04181OTLAA
GA14-4671
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Untitled
Abstract: No abstract text available
Text: ADVANCE M i n P r i M I •■i— i - i h - i i ' w 256K X 18, 128K X 32/36 3.3V I/O, PIPELIN ED , DCD S Y N C B U R S T SR A M MT58LC256K18C6, MT58LC128K32C6, MT58LC128K36C6 SYNCBURST SRAM 3.3V Supply, Pipelined, Burst Counter and Double-Cycle Deselect SYNCBURST SRAM
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MT58LC256K18C6,
MT58LC128K32C6,
MT58LC128K36C6
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"absg"
Abstract: No abstract text available
Text: 64Kx18 Synchronous SRAM KM718V687 64Kx18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION • • • • • • • • • • • The KM718V687 is a 1,179,648 bits Synchronous Static Ran dom Access Memory designed to support zero wait state per
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KM718V687
64Kx18-Bit
100-TQFP-1420A
64Kx18
KM718V687
"absg"
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5-pen pc technology
Abstract: No abstract text available
Text: 32Kx32 Synchronous SRAM KM732V599A/L 32Kx32-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • 2Stage Pipelined operation with 4Burst. • On-Chip Address Counter. The KM732V599A/L is a 1,048,576-bit Synchronous Static
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KM732V599A/L
32Kx32
32Kx32-Bit
KM732V599A/L
576-bit
5-pen pc technology
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XC5L
Abstract: No abstract text available
Text: KMM466S204CT 144pin SDRAM SODIMM KMM466S204CT SDRAM SODIMM 2Mx64 SDRAM SODIMM based on 1Mx16,4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM466S204CT Is a 2M bit x 64 Synchronous Dynamic RAM high density memory module. The SamsunQ
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KMM466S204CT
KMM466S204CT
144pin
2Mx64
1Mx16
KMM486S204CT
400mII
144-pin
XC5L
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Untitled
Abstract: No abstract text available
Text: KM736V687 64Kx36 Synchronous SRAM 64Kx36-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION • • • • • • • ■ • • • • The KM736V687 is 2,359,296 bits Synchronous Static Random Access Memory designed to support zero wait state perfor
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KM736V687
64Kx36-Bit
100-TQFP-1420A
64Kx36
KM736V687
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PC2500AH
Abstract: PC2500 12-pin stereo amplifier GD4C5423 22NEC UPC2500A
Text: PRELIMINARY DATA SHEET b42752S DOHTMES 340 • NECE BIPOLAR ANALOG INTEGRATED CIRCUIT ELECTRON DEVICE M PC2500A 45 W AF POWER AMPLIFIER DESCRIPTION The ;iPC2500A is an audio power amplifier in a 12-lead single in-line package, specifically designed for car stereo appli
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b42752S
uPC2500A
iPC2500A
12-lead
PC2500A
P12HP-254B2
323-Oou
PC2500AH
PC2500
12-pin stereo amplifier
GD4C5423
22NEC
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m5m5v1132
Abstract: M5M5V1132A m5m5v1132agp
Text: MITSUBISHI LSIs P R E U W " n ” M 5 M 5 V 1 1 3 2 A F P ,G P - 3 ,-4 ,- 6 ,- 7 ,-8 _ 1048576-BIT 32766-WQRD BY 32-BIT SYNCHRONOUS BURST SRAM DESCRIPTION The M5M5V1132A Is a family of 1M bit synchronous SRAMs organized as 32768-words of 32-bit. The M5M5V1132A provides a
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1048576-BIT
32766-WQRD
32-BIT)
M5M5V1132A
32768-words
32-bit.
m5m5v1132
m5m5v1132agp
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Untitled
Abstract: No abstract text available
Text: S â fllb b Z G ÜEISbD 3Tb PRELIMINARY CY2278A Pentium and Pentium II™ Compatible Clock Synthesizer/Driver for Mobile PCs Features Functional Description • Mixed 2.5V and 3.3V operation • Complete clock solution to meet requirements of mo bile Pentium™ and Pentium II™ motherboards
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CY2278A
CY2278A
82430TX
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