r727
Abstract: No abstract text available
Text: User's Guide SLLU180 – June 2013 TLK10232 Dual-Channel XAUI/10GBASE-KR Transceiver with Crosspoint Evaluation Module EVM Graphical Users Interface User’s Guide This user’s guide describes the usage and construction of the TLK10232 evaluation module (EVM). This
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SLLU180
TLK10232
XAUI/10GBASE-KR
r727
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manual motherboard canada ices 003 class b
Abstract: motherboard canada ices 003 class b g31 motherboard manual motherboard canada ices 003 class a manual motherboard canada ices 003 class b user
Text: User's Guide SLLU168 – August 2012 TLK10034 Quad-Channel XAUI/10GBASE-KR Transceiver Evaluation Module EVM This user’s guide describes the usage and construction of the TLK10034 evaluation module (EVM). This document provides guidance on proper use by showing some device configurations and test modes. In
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SLLU168
TLK10034
XAUI/10GBASE-KR
manual motherboard canada ices 003 class b
motherboard canada ices 003 class b
g31 motherboard
manual motherboard canada ices 003 class a
manual motherboard canada ices 003 class b user
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88X2040
Abstract: 88X2040-BAN marvell IEEE free download capacitor data sheet Marvell 8001 xaui evaluation board
Text: LatticeECP2M Marvell XAUI 10 Gbps Physical Layer Interoperability November 2008 Technical Note TN1191 Introduction This technical note describes a physical layer 10 Gigabit Ethernet XAUI 10 Gbps interoperability test between a LatticeECP2M FPGA and the Marvell Alaska 88X2040 device. The test was limited to the physical layer (up to
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TN1191
88X2040
10-Gigabit
1-800-LATTICE
88X2040-BAN
marvell IEEE
free download capacitor data sheet
Marvell 8001
xaui evaluation board
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88X2040
Abstract: 88X2040-BAN xGMII to rj45 phy marvell IEEE 946 motherboard
Text: LatticeECP3 Marvell XAUI 10 Gpbs Physical Layer Interoperability June 2009 Technical Note TN1194 Introduction This technical note describes a physical layer 10-gigabit Ethernet: XAUI 10 Gbps interoperability test between a LatticeECP3 device and the Marvell Alaska 88X2040 device. The test was limited to the physical layer (up to
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TN1194
10-gigabit
88X2040
1-800-LATTICE
88X2040-BAN
xGMII to rj45 phy
marvell IEEE
946 motherboard
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BCM56800
Abstract: XAUI rdbgc0 LFE2M50E TN1188 bcm5680 bcm pause frame BCM 10G BCM0 SFP EVALUATION BOARD 10G
Text: LatticeECP2M Broadcom XAUI 10 Gbps Physical Layer Interoperability Over CX-4 November 2009 Technical Note TN1188 Introduction This technical note describes a physical layer 10 Gigabit Ethernet XAUI 10 Gbps interoperability test between a LatticeECP2M device and the Broadcom BCM56800 network switch. The test was limited to the physical layer
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TN1188
BCM56800
1-800-LATTICE
XAUI
rdbgc0
LFE2M50E
TN1188
bcm5680
bcm pause frame
BCM 10G
BCM0
SFP EVALUATION BOARD 10G
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88X2040
Abstract: XAUI link ip crpa marvell alaska 8B10B Marvell fibre copper marvell alaska registers 88X240-BAN
Text: LatticeSC/Marvell XAUI Interoperability November 2006 Technical Note TN1128 Introduction The document provides a report on a XAUI interoperability test between a LatticeSC device and the Marvell 88X2040 device. Specifically, this technical note discusses the following topics:
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TN1128
88X2040
10-Gigabit
1-800-LATTICE
XAUI link ip
crpa
marvell alaska
8B10B
Marvell fibre copper
marvell alaska registers
88X240-BAN
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higig specification
Abstract: "higig header" BCM56800 bcm pause frame rdbgc0 higig protocol overview IR9216 broadcom bcm BCM0 BCM 10G
Text: LatticeSC/M Broadcom XAUI/HiGig 10 Gbps Physical Layer Interoperability Over CX-4 August 2007 Technical Note TN1155 Introduction This technical note describes a physical layer 10-Gigabit Ethernet and HiGig 10 Gbps interoperability test between a LatticeSC/M device and the Broadcom BCM56800 network switch. The test was limited to the physical
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TN1155
10-Gigabit
BCM56800
1-800-LATTICE
higig specification
"higig header"
bcm pause frame
rdbgc0
higig protocol overview
IR9216
broadcom bcm
BCM0
BCM 10G
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SGMII PCIE bridge
Abstract: RGMII to SGMII bridge SGMII RGMII bridge StrataXGS EVALUATION BOARD 88E1111 Marvell 88E1111 mdio 88E1111 jumbo GMII Marvell PHY 88E1111 Datasheet 88e1111 mii fpga ethernet sgmii
Text: f u l l y t e s t e d a n d i n t e r o p e r a b l e Lattice Ethernet Solutions Ready-to-Use Ethernet Portfolio Lattice provides customers with low cost and low power programmable solutions that are ready-to-use right out of the box. A full suite of tested and interoperable solutions is available for Ethernet
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10GbE,
1-800-LATTICE
LatticeMico32,
I0194B
SGMII PCIE bridge
RGMII to SGMII bridge
SGMII RGMII bridge
StrataXGS
EVALUATION BOARD 88E1111
Marvell 88E1111 mdio
88E1111 jumbo GMII
Marvell PHY 88E1111 Datasheet
88e1111 mii
fpga ethernet sgmii
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TN1176
Abstract: LFE395 alarm clock design of digital verilog IPUG68 CRPAT
Text: LatticeECP3 XAUI Demo Design User’s Guide July 2010 UG23_01.2 LatticeECP3 XAUI Demo Design User’s Guide Lattice Semiconductor Introduction This document provides technical information and instructions on using the LatticeECP3 XAUI Demo Design.
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TN1176.
TN1176
LFE395
alarm clock design of digital verilog
IPUG68
CRPAT
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Untitled
Abstract: No abstract text available
Text: Integrated DeviceTechnology DeviceTechnology Integrated Signal Integrity Products POWER MANAGEMENT | ANALOG & RF | INTERFACE & CONNECTIVITY | CLOCKS & TIMING | MEMORY & LOGIC | TOUCH & USER INTERFACE | VIDEO & DISPLAY | AUDIO TARGET APPLICATIONS Repeaters:
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REVA0311
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"higig header"
Abstract: higig specification higig protocol overview TN1154 cx4 to sma BCM56802 higig pause frame ir9216 BROADCOM higig2
Text: LatticeSC/M Broadcom HiGig+ 12 Gbps Physical Layer Interoperability Over CX-4 August 2007 Technical Note TN1154 Introduction This technical note describes a physical layer HiGig+ 12 Gbps interoperability test between a LatticeSC/M device and the Broadcom BCM56802 network switch. The test was limited to the physical layer up to XGMII of the 10
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TN1154
BCM56802
1-800-LATTICE
"higig header"
higig specification
higig protocol overview
TN1154
cx4 to sma
higig pause frame
ir9216
BROADCOM
higig2
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8b/10b decoder
Abstract: MC860 ORT82G5 ORT82G5-2BM680 ORCA
Text: FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP ORCA ORT82G5 Evaluation Board Evaluate 3.7Gbps SERDES + FPGA Quickly and Easily Making the Right Choice… Choosing the right device to drive 3.7Gbits/s data over your backplane can be a critical decision, but evaluating your options
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ORT82G5
ORT82G5
MC860
ORT82G5.
1-800-LATTICE
8b/10b decoder
MC860
ORT82G5-2BM680
ORCA
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jtag cable lattice Schematic
Abstract: MC860 ORT82G5 ORT82G5-2BM680 the application of fpga in today hsi jtag cable
Text: FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP ORCA ORT82G5 Evaluation Board Evaluate 3.7Gbps SERDES + FPGA Quickly and Easily Making the Right Choice… Choosing the right device to drive 3.7Gbits/s data over your backplane can be a critical decision, but evaluating your options
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ORT82G5
ORT82G5
MC860
ORT82G5.
1-800-LATTICE
I0143
jtag cable lattice Schematic
MC860
ORT82G5-2BM680
the application of fpga in today
hsi jtag cable
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Untitled
Abstract: No abstract text available
Text: BCM8040 PRODUCT Brief 8-CHANNEL MULTI-RATE CMOS RETIMER WITH FULL REDUNDANCY B C M 8 0 4 0 S U M M A R Y F E AT U R E S Eight independent retimers made up of four complete • XGMII eXtender Sublayer cores XGXS that can be SONET (with/without FEC), Infiniband, 10 Gigabit
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BCM8040
10GbE
8040-PB00-R-3
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Abstract: No abstract text available
Text: QorIQ Multicore Processor Development QorIQ P5040 Development System Overview The P5040DS-PA is a flexible development system based on the dual-core 32/64-bit moded P5040 device. The board, with its 2.2 GHz P5040 and rich I/O mix, is intended for evaluation of the QorIQ P5040/
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P5040
P5040DS-PA
32/64-bit
P5040
P5040/
P5021processor
P5040DSFS
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tx 2G transmitter
Abstract: tx 2G 10G BERT 10G serdes bert BCM8040 BCM8702
Text: BCM8040 8-CHANNEL MULTIRATE 1.0–3.2-GBPS RETIMER/SWITCH SUMMARY OF BENEFITS FEATURES • One device supports a variety of applications including • 8 independent retimer channels supporting multiple data rates • • • • • from 1.0 to 3.2 Gbps, including 1.06 Gbps, 1.25 Gbps, 2.12
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BCM8040
IEEE802
10-Gigabit
40-Gbps
8040-PB04-R
tx 2G transmitter
tx 2G
10G BERT
10G serdes bert
BCM8040
BCM8702
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Untitled
Abstract: No abstract text available
Text: BCM8040 QUAD XAUI /CX4/LX4 1.0 - 3.2 Gbps RETIMER/SWITCH SUMMARY OF BENEFITS FEATURES • Eight independent retimer channels supporting multiple data • • • • • rates from 1.0 to 3.2 Gbps, including 1.06 Gbps, 1.25 Gbps, 2.12 Gbps, 2.488 Gbps, 2.5 Gbps, 2.667 Gbps, 3.125 Gbps, and
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BCM8040
IEEE802
10-Gigabit
40-Gbps
8040-PB05-R
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Untitled
Abstract: No abstract text available
Text: BCM8040 PRODUCT Brief 8-CHANNEL MULTIRATE 1.0–3.2-GBPS RETIMER/SWITCH B C M 8 0 4 0 S U M M A R Y F E AT U R E S O F B E N E F I T S • 8 independent retimer channels supporting multiple • One device supports a variety of applications including • Multi-configurable to support various operating modes
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BCM8040
IEEE802
40-Gbps
8040-PB03-R-04-15-03
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HW-AFX-SMA-SFP
Abstract: FPGA UART ML403 XAPP691 ML310 XAPP443 sgmii sfp virtex marvell ethernet switch sgmii ML323 ML401
Text: Application Note: Ethernet Cores Hardware Demonstration Platform Ethernet Cores Hardware Demonstration Platform R XAPP443 v1.0 July 11, 2005 Summary The Ethernet Cores Hardware Demonstration Platform application note describes the functionality of Ethernet cores in Xilinx FPGA hardware. The development board requirements,
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XAPP443
10-Gigabit
UG150,
UG144,
UG155,
UG170,
April28,
UG074,
ML323
UG033
HW-AFX-SMA-SFP
FPGA UART
ML403
XAPP691
ML310
XAPP443
sgmii sfp virtex
marvell ethernet switch sgmii
ML401
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10G BERT
Abstract: CX4 connector BCM8040
Text: BCM8040 QUAD XAUI /CX4/LX4 1.0–3.2-GBPS RETIMER/SWITCH FEATURES • Eight independent retimer channels supporting multiple data • • • • • rates from 1.0 to 3.2 Gbps, including 1.06 Gbps, 1.25 Gbps, 2.12 Gbps, 2.488 Gbps, 2.5 Gbps, 2.667 Gbps, 3.125 Gbps, and
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BCM8040
IEEE802
8040-PB06-R
10G BERT
CX4 connector
BCM8040
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Untitled
Abstract: No abstract text available
Text: BCM8021 10 GbE XAUI TRANSCEIVER WITH HIGH-SPEED REDUNDANCY SUMMARY OF BENEFITS FEATURES • 10GbE Transceiver supporting various operating modes • • • • • • IEEE 802.3ae compliant XAUI to XGMII transceiver • XAUI-to-XAUI retiming Low power dissipation
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BCM8021
10GbE
11Applications
10-Gigabit
8021-PB03-R
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10G CX4
Abstract: CX4 connector cx4 loopback connector tx 2G 10GBASE-CX4 BCM8022 prbs generator
Text: BCM8022 XAUI to 10GBASE-CX4 RETIMER SUMMARY OF BENEFITS FEATURES • Enables low-cost applications transmitting 10GbE over • High-speed Retiming for transmission over copper • • • • • • interconnects such as Infiniband Cables or Backplanes
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BCM8022
10GBASE-CX4
10GbE
10-Gbps
8022-PB01-R
10G CX4
CX4 connector
cx4 loopback connector
tx 2G
BCM8022
prbs generator
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Untitled
Abstract: No abstract text available
Text: BCM8020 PRODUCT Brief 8-CHANNEL MULTI-RATE CMOS TRANSCEIVER WITH FULL REDUNDANCY B C M 8 0 2 0 S U M M A R Y F E AT U R E S Eight Independent Transceivers supporting multiple • data rates from 1.0 Gbps to 3.2 Gbps including 1.0 O F B E N E F I T S One SerDes design supports a variety of applications
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BCM8020
1875Gbps.
OC-48
8020-PB00-R-3
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serdes transceiver
Abstract: BCM8021 applications of prbs generator
Text: BCM8021 10-GbE XAUI TRANSCEIVER WITH HIGH-SPEED REDUNDANCY SUMMARY OF BENEFITS FEATURES • 10-GbE transceiver supporting various operating modes • • • • • • IEEE 802.3™ae-compliant XAUI™ to XGMII transceiver • XAUI-to-XAUI retiming
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BCM8021
10-GbE
114with
IEEE802
8021-PB04-R
serdes transceiver
BCM8021
applications of prbs generator
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