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    XOR FOUR INPUTS Search Results

    XOR FOUR INPUTS Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    DCL541A01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: Low / Input disable Visit Toshiba Electronic Devices & Storage Corporation
    DCL541B01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: High / Input disable Visit Toshiba Electronic Devices & Storage Corporation
    TLX9188 Toshiba Electronic Devices & Storage Corporation Photocoupler (phototransistor output), DC input, 3750 Vrms, SO6, Automotive Visit Toshiba Electronic Devices & Storage Corporation
    TB67H480FNG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=50/Iout(A)=2.5/ PHASE input type Visit Toshiba Electronic Devices & Storage Corporation
    TB67H481FNG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=50/Iout(A)=2.5/ IN input type Visit Toshiba Electronic Devices & Storage Corporation

    XOR FOUR INPUTS Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    7486 XOR GATE pin configuration

    Abstract: No abstract text available
    Text: The Leader in High Temperature Semiconductor Solutions CHT-7486 DATASHEET Revision: 03.3 Oct. 01, 2012 Last Modified Date High-Temperature, Quad 2-Inputs XOR Gate General Description Features The CHT-7486 contains four independent 2-inputs XOR gates, performing the Boolean function :


    Original     		CHT-7486 CDIL14) CSOIC16) DS-080208 7486 XOR GATE pin configuration PDF

    Untitled

    Abstract: No abstract text available
    Text: 1000EA Family Architectural Description four outputs, which can be configured to be either combinatorial or registered. Inputs to the GLB come from the Global Routing Pool GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that


    Original     		1000EA 1016EA, 1024EA, 1032EA 1048EA. 0494/1K t20ptxor) PDF

    1032E

    Abstract: 1032EA SE140 se 140
    Text: ispLSI 1032EA In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original     		1032EA 1032E 100-Pin 0212/1032EA 1032EA-200 1032EA 1032EA-125LT100 1032E SE140 se 140 PDF

    1032E

    Abstract: 1032EA
    Text: ispLSI 1032EA In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original     		1032EA 1032E Logic1032EA 1032EA 100-Pin 0212/1032EA 1032EA-200 1032EA-200LT100 1032E PDF

    1032E

    Abstract: 1032EA
    Text: ispLSI 1032EA In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original     		1032EA 1032E Logic1032EA 1032EA 100-Pin 0212/1032EA 1032EA-200 1032EA-200LT100 1032E PDF

    Untitled

    Abstract: No abstract text available
    Text: ispLSI 1032EA In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original     		1032EA 1032E 1032EA 100-Pin 0212/1032EA 1032EA-200 1032EA-200LT100 PDF

    Untitled

    Abstract: No abstract text available
    Text: 19-2786; Rev 1; 12/03 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ 200Msps Output Update Rate ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -88dBc at fOUT = 10MHz


    Original     		16-Bit, 200Msps 77dBc 10MHz -88dBc 72MHz 48-Pin MAX5885EGM PDF

    MAX5883

    Abstract: MAX5884 MAX5884EGM MAX5885 MAX5886 MAX5887 MAX5888 Best GSM state transition diagram 30.72MHZ
    Text: 19-2825; Rev 0; 4/03 3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -86dBc at fOUT = 10MHz ACLR = 72dB at fOUT = 30.72MHz


    Original     		14-Bit, 200Msps 77dBc 10MHz -86dBc 72MHz 48-Pin MAX5884EGM MAX5884 MAX5883 MAX5884 MAX5884EGM MAX5885 MAX5886 MAX5887 MAX5888 Best GSM state transition diagram 30.72MHZ PDF

    MAX5883

    Abstract: MAX5884 MAX5884EGM MAX5885 MAX5886 MAX5887 MAX5888
    Text: 19-2825; Rev 1; 12/03 3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -86dBc at fOUT = 10MHz ACLR = 72dB at fOUT = 30.72MHz


    Original     		14-Bit, 200Msps 77dBc 10MHz -86dBc 72MHz 48-Pin MAX5884EGM MAX5884 MAX5883 MAX5884 MAX5884EGM MAX5885 MAX5886 MAX5887 MAX5888 PDF

    Untitled

    Abstract: No abstract text available
    Text: 19-2825; Rev 1; 12/03 3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ 200Msps Output Update Rate ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -86dBc at fOUT = 10MHz


    Original     		14-Bit, 200Msps 77dBc 10MHz -86dBc 72MHz 48-Pin MAX5884EGM PDF

    Untitled

    Abstract: No abstract text available
    Text: 19-2786; Rev 1; 12/03 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -88dBc at fOUT = 10MHz ACLR = 74dB at fOUT = 30.72MHz


    Original     		16-Bit, 200Msps MAX5885 77dBc 10MHz. 200mW. PDF

    Untitled

    Abstract: No abstract text available
    Text: 19-2825; Rev 1; 12/03 3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -86dBc at fOUT = 10MHz ACLR = 72dB at fOUT = 30.72MHz


    Original     		14-Bit, 200Msps MAX5884 77dBc 10MHz. 200mW. PDF

    MAX5883

    Abstract: MAX5884 MAX5885 MAX5885EGM MAX5886 BTS gsm850
    Text: 19-2786; Rev 0; 4/03 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -88dBc at fOUT = 10MHz ACLR = 74dB at fOUT = 30.72MHz


    Original     		16-Bit, 200Msps 77dBc 10MHz -88dBc 72MHz 48-Pin MAX5885EGM MAX5885 MAX5883 MAX5884 MAX5885 MAX5885EGM MAX5886 BTS gsm850 PDF

    MAX5885

    Abstract: BTS Base Terminal Station MAX5883 MAX5884 MAX5885EGM MAX5886
    Text: 19-2786; Rev 1; 12/03 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -88dBc at fOUT = 10MHz ACLR = 74dB at fOUT = 30.72MHz


    Original     		16-Bit, 200Msps 77dBc 10MHz -88dBc 72MHz 48-Pin MAX5885EGM MAX5885 MAX5885 BTS Base Terminal Station MAX5883 MAX5884 MAX5885EGM MAX5886 PDF

    1032E

    Abstract: 1032EA
    Text: ispLSI 1032EA In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original     		1032EA 1032E 100-TQFP/1032EA 1032EA 100-Pin 0212/1032EA 1032EA-200LT100 1032E PDF

    QFN-48 LAND PATTERN

    Abstract: No abstract text available
    Text: 19-2825; Rev 1; 12/03 3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -86dBc at fOUT = 10MHz ACLR = 72dB at fOUT = 30.72MHz


    Original     		14-Bit, 200Msps MAX5884 77dBc 10MHz. 200mW. QFN-48 LAND PATTERN PDF

    QFN-48 footprint

    Abstract: QFN-48 LAND PATTERN
    Text: 19-2786; Rev 1; 12/03 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz to Nyquist IMD = -88dBc at fOUT = 10MHz ACLR = 74dB at fOUT = 30.72MHz


    Original     		16-Bit, 200Msps MAX5885 77dBc 10MHz. 200mW. QFN-48 footprint QFN-48 LAND PATTERN PDF

    Untitled

    Abstract: No abstract text available
    Text: FINAL COM’L: -12.Q-20 Advanced Micro Devices MACH435-12, Q-20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 84 Pins in PLCC ■ Up to 20 product terms per function, with XOR ■ 128 Macrocells ■ Flexible clocking ■ 12nstpD — Four global clock pins with selectable edges


    OCR Scan     		MACH435-12, 12nstpD PAL33V16â MACH130, MACH230 25752b 84-Pin 16-038-S PDF

    Untitled

    Abstract: No abstract text available
    Text: P r o d u c t S p e c if ic a t io n < $ 2 iL G 5 Z8615 NMOS Z8 8-BlT MCI Keybo ard Co n tro ller FEATURES • Low Power Consumption - 750 mW ■ 32 Input/Output Lines ■ Digital Inputs NMOS Levels with Internal Pull-Up Resistors ■ 4 Kbytes ROM ■ Four Direct Connect LED Drive Ports


    OCR Scan     		Z8615 Z8615 Z861505PSC Z861505VSC 003373S PDF

    crc-16 implementation

    Abstract: toggle type flip flop ic
    Text: TEKTRONIX INC/ TRI ÛUINT EbE D Ì[Q G igaB St B ÔTQbSlô QQ00405 4 EiTRÖ 10G024 10G024K L o g ic Quad D Flip Flop with XOR Inputs 1.9 GHz Clock Rate 10G PicoLogic Family_ FEATURES • Temperature and voltage compensated design • < 50 ps clock to output delay skew


    OCR Scan     		QQ00405 10G024 10G024K 10G024K) 10G061 050P3 crc-16 implementation toggle type flip flop ic PDF

    Untitled

    Abstract: No abstract text available
    Text: Lattice p L S r 1016 programmable Large Scale Integration High-Density Programmable Logic Functional Block Diagram Features • PROGRAMMABLE HIGH-DENSITY LOGIC — Member of Lattice’s pLSI Family — High-Speed Global Interconnects — 32 I/O Pins, Four Dedicated Inputs


    OCR Scan     		pLS11016 1016-90LJ 44-Pin 1016-80LJ 1016-60LJI PDF

    Untitled

    Abstract: No abstract text available
    Text: Lattice ispLSr 1016 H I Semiconductor •■■ Corporation In-System Programmable High Density PLD Functional Block Diagram Features • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs


    OCR Scan     		Military/883 44-Pin 1016-80LT44 1016-60LJ 1016-60LT44 1016-60LJI PDF

    Untitled

    Abstract: No abstract text available
    Text: Lattice pLSI 1016/883 programmable Large Scale Integration High-Density Programmable Logic Features Functional Block Diagram • PROGRAMMABLE HIGH-DENSITY LOGIC — — — — — MIL-STD-883 Version of the pLS11016 High-Speed Global Interconnects 32 I/O Pins, Four Dedicated Inputs


    OCR Scan     		MIL-STD-883 pLS11016 44-Pin pLS11016/883 1016-60LH/883 44vPln PDF

    PLSI 1016-60LJ

    Abstract: lattice 1016-60LJ 1016-60LJI LSI1016 1016-60LT44 PLS11016
    Text: Lattice is p L S I Semiconductor Corporation a n d p L S I 1 1 6 High-Density Programmable Logic Features • d lB R I B B E I I d l i H i l B ü l • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs


    OCR Scan     		Military/883 44-Pin 1016-60LT44I 1016-60LJI 1016-60LJI PLSI 1016-60LJ lattice 1016-60LJ LSI1016 1016-60LT44 PLS11016 PDF