74AHCT
Abstract: TTL Schmitt-Trigger cmos BC5-10
Text: Zytrex ZX54AHCT ZX74AHCT February 1985 121 Monostable Multivibrators with Schmitt-Trigger inputs OBJECTIVE SPECIFICATIONS Features Description • Schmitt-trigger for slow input transitions ■ Internal timing resistor These multivibrators feature dual negative-transition-trig
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ZX54AHCT
ZX74AHCT
54/74ALS
74AHCT:
54AHCT:
74AHCT
TTL Schmitt-Trigger
cmos
BC5-10
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bma 023
Abstract: 74AHCT
Text: Zytrex _ F ebruary 1965 OBJECTIVE SPECIFICATIONS Hex Inverter Features Description • Function, pin-out, speed and drive compatibility with 54/74ALS logic family These devices contain six independent inverters. They perform the Boolean function Y = A.
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ZX54AHCT
ZX74AHCT
54/74ALS
74AHCT:
54AHCT:
bma 023
74AHCT
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A7c DIODE
Abstract: 74AHCT 113B8 74als power consumption
Text: Zytrex ZX54AHCT ZX74AHCT 640 ?* "cT643 Octal Bus Transceivers February 1985 OBJECTIVE SPECIFICATIONS . Features Description • Function, pin-out, speed and drive compatibility with 54/74ALS logic family These high-speed octal bus transceivers are designed
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ZX54AHCT
ZX74AHCT
54/74ALS
74AHCT:
54AHCT:
A7c DIODE
74AHCT
113B8
74als power consumption
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74AHCT
Abstract: No abstract text available
Text: Zytrex ZXS4AHCT ZX74AHCT 12 Triple 3-Input NAND Gates with Open-Draln Outputs February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74ALS logic family These devices contain three independent 3-input NAND
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ZX74AHCT
54/74ALS
74AHCT:
54AHCT:
74AHCT
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74HCTLS
Abstract: No abstract text available
Text: Zytrex ZXS4HCTLS ZX74HCTLS February 1985 11 Triple 3-Input AND Gates O BJECTIVE S P E C IF IC A TIO N S Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain three independent 3-input AND
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54/74LS
74HCTLS:
54HCTLS:
ZX54HCTLS
ZX74HCTLS
74HCTLS
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74AHCT
Abstract: No abstract text available
Text: Zytrex ZXS4AHCT ZX74AHCT 05 Hex Inverters with Open-Drain Outputs February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pln-out, speed and drive compatibility with 54/74ALS logic family These devices contain six independent inverters with
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ZX54AHCT
ZX74AHCT
54/74ALS
74AHCT:
54AHCT:
74AHCT
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74HCTLS
Abstract: Zytrex
Text: Zytrex B G W K nS F ebrua ry 1985 646 ZX74HCTLS 648 Octal 3-State Bus Transceivers with Registers OBJECTIVE SPECIFICATIONS Features Description • 8 bi-directional data paths The ’646 and '648 are bi-directional bus transceivers with D-type flip-flops and control circuitry to facilitate high
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ZX54HCTLS
ZX74HCTLS
24-pin
54/74LS
74HCTLS:
54HCTLS:
74HCTLS
Zytrex
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74LS TTL 245
Abstract: 74HCTLS 74hctl PPT Diode specifications
Text: Zytrex ZX54HCTLS ZX74HCTLS February 1985 245 Octal Bus Transceivers with 3-State Outputs OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These high-speed octal bus transceivers are designed
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ZX54HCTLS
ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
74LS TTL 245
74HCTLS
74hctl
PPT Diode specifications
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74HCTLS
Abstract: hctls574 HCTLS
Text: Zytrex ZX54HCTLS ZX74HCTLS February 1985 574 Octal D-Type Flip-Flops with 3-State Outputs OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family ■ Low power consumption characteristic of
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ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
74HCTLS
hctls574
HCTLS
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74AHCT
Abstract: No abstract text available
Text: Zytrex ZXS4AHCT ZX74AHCT 259 8-Bit Addressable Latches February 1985 OBJECTIVE SPECIFICATIONS Features Description • 8-Bit parallel-out storage register performs serial-to-parallel conversion with storage The ’259 is a high-speed addressable latch designed for
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ZX74AHCT
54/74ALS
74AHCT
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hctls299
Abstract: 74HCTLS
Text: Zytrex ZXS4HCTLS ZX74HCTLS February 1985 8-Bit Universal Shift/Storage Registers with 3-State Outputs OBJECTIVE SPECIFICATIONS Features Description • Multiplexed I/O ports provides improved bit density These eight-bit universal registers feature multiplexed
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ZX54HCTLS
ZX74HCTLS
54/74LS
hctls299
74HCTLS
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74hctls
Abstract: No abstract text available
Text: Zytrex ZX54HCTLS ZX74HCTLS 73A Dual J-K Negative-Edge-Triggered Flip-Flops with Clear Februa ry 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain two independent J-K negativeedge-triggered flip-flops. A low level at the CLR input
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ZX54HCTLS
ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
74hctls
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74HCTLS
Abstract: No abstract text available
Text: Zytrex ZXS4HCTLS ZX74HCTLS Februa ry 1985 74A Dual D-Type Positive-Edge-Triggered Flip-Flops with Preset and Clear OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain two independent positive-edgetriggered D-type flip-flops. Each flip-flop has its own
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ZX54HCTLS
ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
ZX74HCTLS
74HCTLS
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Zytrex 74ahct
Abstract: 74AHCT
Text: Zytrex ZXS4AHCT ZX74AHCT 138 3-Line to 8-Line Decoders/Multiplexers February 1985 OBJECTIVE SPECIFICATIONS . Features Description • Designed specifically for high-speed memory decoders and data transmission systems These devices are designed to be used in high-perform
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ZX74AHCT
54/74ALS
74AHCT:
54AHCT:
74AHCT
Ta--40Â
Ta--55Â
Zytrex 74ahct
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74HCTLS
Abstract: No abstract text available
Text: Zytrex ZX54HCTLS ZX74HCTLS February 1985 273 Octal D-Type Flip-Flops with Clear OBJECTIVE SPECIFICATIONS Features Description • Eight positive-edge-triggered D-type flipflops with single-rail outputs these devices are high-speed octal registers. They con
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ZX54HCTLS
ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
74HCTLS
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74AHCT
Abstract: 74als power consumption Zytrex
Text: Zytrex _ Fe brua ry 1985 ZXS4AHCT ZX74AHCT # # S m^ Dual Retriggerable Monostable Multivibrator OBJECTIVE SPECIFICATIONS Features Description • Simple pulse width formula T = RC The '123 consists of two independent monostable multi vibrators that feature both a negative, A, and a positive,
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54/74ALS
74AHCT:
54AHCT:
ZX74AHCT
74AHCT
74als power consumption
Zytrex
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8D-13
Abstract: 74AHCT
Text: Zytrex ZXS4AHCT ZX74AHCT 374 Octal D-Type Flip-Flops with 3-State Outputs February 1985 OBJECTIVE SPECIFICATIONS Features Description m Function, pin-out, speed and drive • Low power consumption characteristic of CMOS The ’374 consists of 8 high-speed D-type edge-triggered
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ZX54AHCT
ZX74AHCT
54/74ALS
74AHCT:
54AHCT:
8D-13
74AHCT
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74AHCT
Abstract: No abstract text available
Text: Zytrex ZXS4AHCT ZX74AHCT February 1985 « % Q u ad 2 -fn p u t O R GatèsL OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74ALS logic family These devices contain four independent 2-input OR gates. They perform the Boolean functions Y = A + B
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ZX54AHCT
ZX74AHCT
54/74ALS
74AHCT:
54AHCT:
74AHCT
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74HCTLS
Abstract: latch 74ls 373
Text: Zytrex February 1985 OBJECTIVE SPECIFICATIONS ZX54HCTLS ZX74HCTLS 563 Octal D-Type Transparent Latches with 3-State Outputs Features Description • 8 latches in a single package The '563 consists of 8 high-speed D-type latches cou pled to 3-state output buffers with high drive current ca
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ZX54HCTLS
ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
74HCTLS
latch 74ls 373
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74AHCT
Abstract: No abstract text available
Text: Zytrex ZXS4AHCT ZX74AHCT Dual 2-to-4 Line Decoder/Multiplexers F e b ru a ry 1 9 8 5 O B J E C T IV E S P E C IF IC A T IO N S 155 . Features Description • Typical applications: Dual 2-to-4 line decoder Dual 1-to-4 line demultiplexer 3-to-8 line decoder
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ZX54AHCT
ZX74AHCT
54/74ALS
74AHCT:
54AHCT:
ahcti55
74AHCT
54AHCT
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74HCTLS
Abstract: diode S4 596
Text: Zytrex ZX54HCTLS ZX74HCTLS February 1985 191 Synchronous 4-Bit Up/Down Binary Counters OBJECTIVE SPECIFICATIONS Features tion e lim in ates the o u tp u t co u n tin g s p ike s no rm a lly a s s o ciate d w ith a syn ch ro n o u s rip ple clo ck cou nters.
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ZX74HCTLS
S4/74LS
74HCTLS:
54HCTLS:
74HCTLS
diode S4 596
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74HCTLS
Abstract: No abstract text available
Text: Z y t r e ZXS4HCTLS § § ZX74HCTLS M x February 1985 Dual J-K Positive Edge-Triggered Flip-Flops with Preset and Clear OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain two positive-edge-triggered J-K
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ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
74HCTLS
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Zytrex
Abstract: 74HCTLS
Text: Z v tr e x #£ ZX54HCTLS ZX74HCTLS Ë Fe brua ry 1965 1 T W M 8-Line to 3-Line Priority Encoders OBJECTIVE SPECIFICATIONS Features Description m Encodes eight data lines In priority The '148 provides three bits of binary coded output rep resenting the position of the highest order active input,
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ZX54HCTLS
ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
Zytrex
74HCTLS
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diode Rl 257
Abstract: Zytrex 74ahct AHCT257 54AHCT Zytrex 74AHCT PF1016
Text: Zvtrex ZXS4AHCT ZX74AHCT 257 ^ 258 Quad 2-Line to 1-Line Data Selector/ Multiplexers with 3-State Outputs February 1985 OBJECTIVE SPECIFICATIONS Description Features Function, pin-out, speed and drive compatibility with 54/74ALS logic family Low power consumption characteristic of
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ZX74AHCT
54/74ALS
74AHCT:
54AHCT:
diode Rl 257
Zytrex 74ahct
AHCT257
54AHCT
Zytrex
74AHCT
PF1016
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