74HCT112PW,112 datasheet
by NXP Semiconductors
- dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; F<sub>max</sub>: 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V; Package: SOT403-1 (TSSOP16); Container: Tube
- Original
- Yes
- Unknown
- Transferred
-
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