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    CY7C1372D-167AXIT datasheet by Cypress Semiconductor

    • 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
    • Original
    • Yes
    • Yes
    • Obsolete
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    CY7C1372D-167AXIT datasheet preview

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