DASF0038403.pdf by Cypress Semiconductor

Partial File Text CY7C1326H 2-Mbit (128K x 18) Pipelined Sync SRAM Functional Description[1] Features · Registered inputs and outputs for pipelined operation · 128K × 18 common I/O architecture · 3.3V core po
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CY7C1326H CY7C1326H-166AXC