DSA00388364.pdf by Xilinx

Partial File Text Application Note: Virtex-4 FX Family Accelerated System Performance with the APU Controller and XtremeDSP Slices R XAPP717 (v1.1.1) Sept. 29, 2005 Author: Harn Hua Ng and Latha Pillai
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APU FCM DSP48 DSP48 floating point IDCT xilinx image rotation verilog ML403 ML403 vga PCORE PPC405 UART ml403 UG073 UG082 verilog code for image rotation verilog code for matrix multiplication verilog for 8 point dct in xilinx vhdl vga Virtex-4 Platform FPGAs TFT XAPP717 Xint32