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    74AUP2G00GT Search Results

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    74AUP2G00GT Price and Stock

    Nexperia 74AUP2G00GT,115

    IC GATE NAND 2CH 2-INP 8XSON
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    DigiKey 74AUP2G00GT,115 Digi-Reel 4,970 1
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    74AUP2G00GT,115 Cut Tape 4,970 1
    • 1 $0.25
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    74AUP2G00GT,115 Reel 5,000
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    Avnet Americas 74AUP2G00GT,115 Reel 6 Weeks 10,000
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    Mouser Electronics 74AUP2G00GT,115
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    Verical 74AUP2G00GT,115 78,940 5,068
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    74AUP2G00GT,115 60,000 5,068
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    Rochester Electronics 74AUP2G00GT,115 138,940 1
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    TTI 74AUP2G00GT,115 Reel 5,000
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    Avnet Asia 74AUP2G00GT,115 20,000 6 Weeks 10,000
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    Avnet Silica 74AUP2G00GT,115 8 Weeks 5,000
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    Rochester Electronics LLC 74AUP2G00GT,115

    IC GATE NAND
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    DigiKey 74AUP2G00GT,115 Bulk 4,139
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    NXP Semiconductors 74AUP2G00GT,115

    NAND Gate 2-Element 2-IN CMOS 8-Pin XSON T/R
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    Verical 74AUP2G00GT,115 40,000 5,068
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    Rochester Electronics 74AUP2G00GT,115 42,000 1
    • 1 $0.0697
    • 10 $0.0697
    • 100 $0.0655
    • 1000 $0.0592
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    Nexperia 74AUP2G00GT

    NAND GATE; Temperature Grade: AUTOMOTIVE; Terminal Form: NO LEAD; No. of Terminals: 8; Package Code: VSON; Package Shape: RECTANGULAR;
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    Vyrian 74AUP2G00GT 157
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    74AUP2G00GT Datasheets (6)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74AUP2G00GT NXP Semiconductors low-power dual 2-input NAND gate Original PDF
    74AUP2G00GT Philips Semiconductors Low-power dual 2-input NAND gate Original PDF
    74AUP2G00GT,115 NXP Semiconductors Low-power dual 2-input NAND gate; Package: SOT833-1 (XSON8U); Container: Reel Pack, SMD, 7" Original PDF
    74AUP2G00GT,115 NXP Semiconductors 74AUP2G00 - IC AUP/ULP/V SERIES, DUAL 2-INPUT NAND GATE, PDSO8, 1 X 1.95 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT833-1, XSON-8, Gate Original PDF
    74AUP2G00GT-G NXP Semiconductors Low-power dual 2-input NAND gate Original PDF
    74AUP2G00GT-G NXP Semiconductors 74AUP2G00GT - Low-power dual 2-input NAND gate Original PDF

    74AUP2G00GT Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    74AUP2G00DC

    Abstract: 74AUP2G00 74AUP2G00GM 74AUP2G00GT MO-187
    Text: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 01 — 25 August 2006 Product data sheet 1. General description The 74AUP2G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall


    Original     		74AUP2G00 74AUP2G00 74AUP2G00. 74AUP2G00DC 74AUP2G00GM 74AUP2G00GT MO-187 PDF

    74aup2g00dc

    Abstract: No abstract text available
    Text: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 02 — 15 May 2007 Product data sheet 1. General description The 74AUP2G00 provides the dual 2-input NAND function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall


    Original     		74AUP2G00 74AUP2G00 74aup2g00dc PDF

    74aup2g00dc

    Abstract: No abstract text available
    Text: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 6 — 1 December 2011 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NAND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall


    Original     		74AUP2G00 74AUP2G00 74aup2g00dc PDF

    74AUP2G00DC

    Abstract: 74AUP2G00 74AUP2G00GT JESD78
    Text: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 5 — 21 October 2010 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NAND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall


    Original     		74AUP2G00 74AUP2G00 74AUP2G00DC 74AUP2G00GT JESD78 PDF

    74aup2g00dc

    Abstract: No abstract text available
    Text: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 03 — 3 April 2008 Product data sheet 1. General description The 74AUP2G00 provides the dual 2-input NAND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall


    Original     		74AUP2G00 74AUP2G00 74aup2g00dc PDF

    74AUP2G00DC

    Abstract: 74AUP2G00 74AUP2G00GD 74AUP2G00GT JESD22-A114E JESD78
    Text: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 04 — 5 June 2008 Product data sheet 1. General description The 74AUP2G00 provides the dual 2-input NAND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall


    Original     		74AUP2G00 74AUP2G00 74AUP2G00DC 74AUP2G00GD 74AUP2G00GT JESD22-A114E JESD78 PDF

    74aup2g00dc

    Abstract: No abstract text available
    Text: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 7 — 8 June 2012 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NAND function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.


    Original     		74AUP2G00 74AUP2G00 74aup2g00dc PDF

    Untitled

    Abstract: No abstract text available
    Text: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 7 — 8 June 2012 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NAND function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.


    Original     		74AUP2G00 74AUP2G00 PDF

    74aup2g00dc

    Abstract: No abstract text available
    Text: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 8 — 5 February 2013 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NAND function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall


    Original     		74AUP2G00 74AUP2G00 74aup2g00dc PDF