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    74LVC3G04DC Search Results

    74LVC3G04DC Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SN74LVC3G04DCUR Texas Instruments Triple Inverter Gate 8-VSSOP -40 to 125 Visit Texas Instruments Buy
    SN74LVC3G04DCURG4 Texas Instruments Triple Inverter Gate 8-VSSOP -40 to 125 Visit Texas Instruments Buy
    SN74LVC3G04DCTRG4 Texas Instruments Triple Inverter Gate 8-SM8 -40 to 125 Visit Texas Instruments Buy
    SN74LVC3G04DCTR Texas Instruments Triple Inverter Gate 8-SM8 -40 to 125 Visit Texas Instruments Buy
    SN74LVC3G04DCUT Texas Instruments Triple Inverter Gate 8-VSSOP -40 to 125 Visit Texas Instruments Buy
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    74LVC3G04DC Price and Stock

    Texas Instruments SN74LVC3G04DCUT

    IC INVERTER 3CH 3-INP 8VSSOP
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    DigiKey SN74LVC3G04DCUT Cut Tape 36,642 1
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    Texas Instruments SN74LVC3G04DCUR

    IC INVERTER 3CH 3-INP 8VSSOP
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    Texas Instruments SN74LVC3G04DCT3

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    74LVC3G04DC Datasheets (6)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74LVC3G04DC Philips Semiconductors Triple inverter Original PDF
    74LVC3G04DC,125 NXP Semiconductors 74LVC3G04 - IC LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8, 2.30 MM, PLASTIC, MO-187, SOT765-1, VSSOP-8, Gate Original PDF
    74LVC3G04DC,125 NXP Semiconductors Triple inverter - Description: 3.3V Triple PicoGate Inverter ; Logic switching levels: TTL ; Number of pins: 8 ; Output drive capability: +/- 32 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: [email protected] ns; Voltage: 1.65-5.5; Package: SOT765-1 (VSSOP8); Container: Reel Pack, Reverse, Reverse Original PDF
    74LVC3G04DC-G NXP Semiconductors 74LVC3G04DC - Triple inverter - Description: 3.3V Triple PicoGate Inverter ; Logic switching levels: TTL ; Number of pins: 8 ; Output drive capability: +/- 32 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: [email protected] ns; Voltage: 1.65-5.5 Original PDF
    74LVC3G04DC-G NXP Semiconductors Triple inverter - Description: 3.3V Triple PicoGate Inverter ; Logic switching levels: TTL ; Number of pins: 8 ; Output drive capability: +/- 32 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: [email protected] ns; Voltage: 1.65-5.5 Original PDF
    74LVC3G04DC-Q100H NXP Semiconductors 74LVC3G04DC-Q100 - 74LVC3G04DC-Q100 - Triple inverter Original PDF

    74LVC3G04DC Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G04 Triple inverter Rev. 10 — 14 June 2012 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC3G04 74LVC3G04

    MO-187

    Abstract: 74LVC3G04 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT JESD22-A114E
    Text: 74LVC3G04 Triple inverter Rev. 05 — 5 October 2007 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC3G04 74LVC3G04 MO-187 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT JESD22-A114E

    Untitled

    Abstract: No abstract text available
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC3G04 Triple inverter Preliminary specification File under Integrated Circuits, IC24 2003 Aug 19 Philips Semiconductors Preliminary specification Triple inverter 74LVC3G04 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 to 5.5 V


    Original     		PDF 74LVC3G04 JESD8B/JESD36 EIA/JESD22-A114-A EIA/JESD22-A115-A OT505-2 OT765-1

    74LVC3G04

    Abstract: 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT JESD22-A114E MO-187
    Text: 74LVC3G04 Triple inverter Rev. 07 — 16 June 2008 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC3G04 74LVC3G04 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT JESD22-A114E MO-187

    marking code E2 logic gate

    Abstract: SN74LVC3G04DCUR 74AUP3G04 74LVC3G04 NC7NP04 NC7NZ04 NL37WZ04 SN74LVC3G04 "MARKING CODE" 3Y
    Text: SLG74LB3G04 GreenLIBTM TRIPLE INVERTER GATE General Description Features The GreenLIB provides the triple inverter gate. This device is • Pb-Free / RoHS Compliant fully specified for partial-power-down applications using Ioff. • Halogen-Free The Ioff circuitry disables the outputs, preventing damaging


    Original     		PDF SLG74LB3G04 000-0074LB3G04-10 marking code E2 logic gate SN74LVC3G04DCUR 74AUP3G04 74LVC3G04 NC7NP04 NC7NZ04 NL37WZ04 SN74LVC3G04 "MARKING CODE" 3Y

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G04 Triple inverter Rev. 10 — 14 June 2012 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC3G04 74LVC3G04

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G04 Triple inverter Rev. 11 — 2 April 2013 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC3G04 74LVC3G04

    74LVC3G04

    Abstract: 74LVC3G04DC 74LVC3G04DP MO-187
    Text: 74LVC3G04 Triple inverter Rev. 01 — 4 May 2004 Product data sheet 1. General description The 74LVC3G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these


    Original     		PDF 74LVC3G04 74LVC3G04 74LVC3G04DC 74LVC3G04DP MO-187

    SOT-833

    Abstract: No abstract text available
    Text: 74LVC3G04 Triple inverter Rev. 04 — 20 March 2007 Product data sheet 1. General description The 74LVC3G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these


    Original     		PDF 74LVC3G04 74LVC3G04 SOT-833

    74LVC3G04

    Abstract: 74LVC3G04DC 74LVC3G04DP 74LVC3G04GT MO-187
    Text: 74LVC3G04 Triple inverter Rev. 03 — 01 February 2005 Product data sheet 1. General description The 74LVC3G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these


    Original     		PDF 74LVC3G04 74LVC3G04 74LVC3G04DC 74LVC3G04DP 74LVC3G04GT MO-187

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G04 Triple inverter Rev. 9 — 23 November 2011 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC3G04 74LVC3G04

    74LVC3G04

    Abstract: 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT
    Text: 74LVC3G04 Triple inverter Rev. 8 — 10 November 2010 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC3G04 74LVC3G04 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT

    74LVC3G04-Q100

    Abstract: No abstract text available
    Text: 74LVC3G04-Q100 Triple inverter Rev. 1 — 14 May 2013 Product data sheet 1. General description The 74LVC3G04-Q100 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC3G04-Q100 74LVC3G04-Q100 AEC-Q10. 74LVC3G04

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G04 Triple inverter Rev. 02 — 18 October 2004 Product data sheet 1. General description The 74LVC3G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these


    Original     		PDF 74LVC3G04 74LVC3G04