CY7C1910KV18 Search Results

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Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310KV18 – 2 M x 8 ■ 333 MHz clock for high bandwidth	Original	18-Mbit CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 CY7C1310KV18 CY7C1910KV18 CY7C1312KV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions	Original	CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit CY7C1310KV18 CY7C1312KV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions	Original	18-Mbit CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 CY7C1310KV18 CY7C1910KV18 CY7C1312KV18	PDF
CY7C1312KV18-250BZXC Abstract: No abstract text available Text: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions	Original	18-Mbit CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 CY7C1310KV18 CY7C1910KV18 CY7C1312KV18 CY7C1312KV18-250BZXC	PDF
Untitled Abstract: No abstract text available Text: CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18	Original	18-Mbit CY7C1312KV18, CY7C1314KV18 CY7C1312KV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Configurations Features Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18	Original	CY7C1312KV18, CY7C1314KV18 18-Mbit CY7C1312KV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1312KV18/CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18	Original	CY7C1312KV18/CY7C1314KV18 18-Mbit CY7C1312KV18	PDF