TAA 611 T12
Abstract: x48 chipset IDT72T6360 IDT72T6480 D25N3
Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag
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Original
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128Mb
256Mb
BB324)
72T6480
drw45
TAA 611 T12
x48 chipset
IDT72T6360
IDT72T6480
D25N3
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PDF
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Untitled
Abstract: No abstract text available
Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 36 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag
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Original
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128Mb
256Mb
BB324)
72T6360
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PDF
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Untitled
Abstract: No abstract text available
Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag
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Original
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128Mb
256Mb
BB324)
72T6480
drw45
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PDF
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TAA 611 T12
Abstract: 72T6480 BA1-B11 d25n3 BA0-C11 k4h561638f A11-C10 q35t Q35T1 A7D9
Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag
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Original
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128Mb
256Mb
drw44
BB324)
72T6480
drw45
TAA 611 T12
72T6480
BA1-B11
d25n3
BA0-C11
k4h561638f
A11-C10
q35t
Q35T1
A7D9
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PDF
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72T6480
Abstract: dsc-6358 IDT72T6360 IDT72T6480 D2312
Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag
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Original
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128Mb
256Mb
133MHz
IDT72T6480
x48in
x48out
x24out
x12out
72T6480
dsc-6358
IDT72T6360
IDT72T6480
D2312
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PDF
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1MD45
Abstract: cy17 High-Zt11-12 CY10 CY82C691 CY82C692 CY82C693 DQ23P cy82
Text: PRELIM INARY CY82C692 W CYPRESS Pentium hyperCache™ Chipset Data-Path Controller with Integrated Cache Features • Supports ail 3.3V Pentium™-class processors, AMD K5, K6 and Cyrix M1 CPUs • Two-bit wraparound counter supporting Intel Burst or Linear burst sequence
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CY82C692
CY82C691
CY82C693
64-bit
128-KB)
55fiTbbE
1MD45
cy17
High-Zt11-12
CY10
CY82C692
DQ23P
cy82
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PDF
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Untitled
Abstract: No abstract text available
Text: IBM14N1372 IBM14N3272 IBM14N6472 High Perform ance SRAM Modules Features • 256K, 512K, and 1MB secondary cache module family using Synchronous and Asynchronous SRAMs. • Organized as a 32K, 64K, or 128K x 72 package on a 4.3” x 1.1”, 160-lead, Dual Read-out DIMM
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IBM14N1372
IBM14N3272
IBM14N6472
160-lead,
i486/PentiumTM
50MHz
66MHz
256KB,
512KB,
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PDF
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Untitled
Abstract: No abstract text available
Text: JÊL S» 1993 ADVANCE M IC R O N I .w r ^ w . ^ MT58LC64K18B2 64K x 18 SYNCHRONOUS SRAM SYNCHRONOUS SRAM 64Kx 18 SRAM +3.3V SUPPLY WITH CLOCKED, REGISTERED INPUTS AND BURST COUNTER FEATURES • • • • • • • • • • • • Fast access times: 9 ,1 0 ,1 2 and 17ns
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MT58LC64K18B2
MT58LC64K18B2EJ-12
MTMLC64K18B2
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PDF
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Untitled
Abstract: No abstract text available
Text: JIH s e 1993 ADVANCE M IC R O N I 64K SEMICONDUCTOR HC SYNCHRONOUS SRAM MT58LC64K18P3 18 SYNCHRONOUS SRAM X 6 4 K x 18 SRAM +3.3V SUPPLY, FULLY REGISTERED INPUTS AND OUTPUTS FEATURES • • • • • • • • • • • • Fast access times: 7 , 10 ,12 and 15ns
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MT58LC64K18P3
52-Pin
MTS8LC64K1BP3
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PDF
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BQ4025
Abstract: bq4025Y
Text: bq4025/bq4025Y BENCHM ARQ 256Kx16 Nonvolatile SRAM Features General Description ► D ata retention in th e absence of power The CMOS bq4025 is a nonvolatile 4,194,304-bit static RAM organized as 262,144 w ords by 16 bits. The in teg ral control circuitry an d lith
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bq4025/bq4025Y
256Kx16
bq4025
304-bit
128Kx
bq4025Y
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PDF
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Untitled
Abstract: No abstract text available
Text: = = = = = = PreMmlnäry IB M 0 4 1 8 1 3 P Q K 64K X 18 B U R S T P I P E L I N E S R A M Features • 64K x 18 Organization • Registered Addresses, Data Ins, Control sig nals, and Outputs • 0.5fi CMOS Technology • Asynchronous Output Enable • Synchronous Burst Mode ot Operation Compati
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i486TM
10OMHz
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PDF
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Untitled
Abstract: No abstract text available
Text: HY UN DA I 64K X HY6718100/101 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x 18 SRAM core, address registers, data input registers, a 2-bit burst address counter and pipelined output. All synchronous inputs pass through registers controlled by a positive-edge
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HY6718100/101
486/Pentium
6ns/9ns/12ns
75MHz
486/Pentlum
1DH01-22-MAY95
HY6718100/101
1DH01-22-MAY9S
HY6718100C
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PDF
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Untitled
Abstract: No abstract text available
Text: •HYUNDAI HY67V16100/101 64K X 16 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64Kx16 SRAM core, address registers, data input registers, a 2-bit burst address counter and pipelined output. All synchronous inputs pass through registers controlled by a positive-edge
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HY67V16100/101
64Kx16
486/Pentium
7ns/12ns/17ns
67MHz
1DH06-11-MAY95
HY67V16100/101
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PDF
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M27C4002
Abstract: M27V402 Q0-Q15
Text: ¿ = 7 S C S -TH O M S O N ^ 7# » EfflD g[Hì(Q lIiL[|(gTniì(o)l] Ì M27V402 LOW VOLTAGE 4 Megabit (256K x 16) UV EPROM and OTP EPROM PRELIMINARY DATA i LOW VOLTAGE READ OPERATION: 3V to 5.5V FAST ACCESS TIME: 120ns LOW POWER ’’CMOS” CONSUMPTION:
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M27V402
120ns
24sec.
M27V402
M27C4002
TSOP40-
Q0-Q15
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PDF
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Untitled
Abstract: No abstract text available
Text: PRELIM INARY CY82C692 Pentium hyperCache™ Chipset Data-Path Controller with Integrated Cache Features • Supports ail 3.3V Pentium™-class processors, AMD K5, K6 and Cyrix M1 CPUs • Two-bit wraparound counter supporting Intel Burst or Linear burst sequence
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OCR Scan
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CY82C692
CY82C691
CY82C693
64-bit
CY82C691
128-KB)
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PDF
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Untitled
Abstract: No abstract text available
Text: HY51V18165B Series •HYUNDAI 1M X 16-bit CMOS DRAM with Burst EDO PRELIMINARY DESCRIPTION The HY51V18165B is the new generation and fast dynamic RAM organized 1,048,576 x 16-bit. The HY51V118165B utilized Hyundai's C M O S silicon gate process technology as well as advenced circuit techniques
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HY51V18165B
16-bit
16-bit.
HY51V118165B
1AD63-00-MAY95
HY51V18165BJC
HY51V18165BTC
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PDF
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Untitled
Abstract: No abstract text available
Text: JUL S 9 1983 ADVANCE llilll— p n M I MT58LC64K18A6 64Kx 18 SYNCHRONOUS SRAM SYNCHRONOUS 64K x 18 SRAM g n r tlV I + 3 -3V SUPPLY, FULLY REGISTERED I/O AND LINEAR BURST COUNTER QR AM FEATURES • • • • • • • • • • • • • Fast access times: 7,10,12 and 15ns
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MT58LC64K18A6
MT58LC64K18A6EJ-10
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PDF
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Untitled
Abstract: No abstract text available
Text: SGS-THOMSON M27V402 R f f lD ^ [ llL liO T IjîO ll i LOW VOLTAGE _ 4 Megabit 256K x 16 UV EPROM and OTP EPROM PRELIMINARY DATA • LOW VOLTAGE READ OPERATION: 3V to 5.5V ■ FAST ACCESS TIME: 120ns ■ LOW POW ER ’’CMOS” CONSUMPTION:
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M27V402
120ns
24sec.
M27V402
M27C4002
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PDF
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Untitled
Abstract: No abstract text available
Text: unir n «i nim ii i mui i iiiij.j.m u i.HHiHnj; MICRON TECHNOLOGY INC b lllS H T 3flE D QG0SÖ73 S • MRN ADVANCE T 'H L -2Z - H 16K x 16 SRAM SRAM WITH A D D R E SS / DATA INPUT LATCHES a FEATURES • • • • • • • • • PIN A SSIG N M EN T Top View)
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T-46-23-14
00G20Ã
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PDF
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Untitled
Abstract: No abstract text available
Text: HY6718110/111 HYUNDAI 64K X 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x18 SRAM core, address registers, data input registers, a 2-bit burst address counter and Non-pipelined output. All synchronous inputs pass through registers controlled by a
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HY6718110/111
486/Pentium
15ns/20ns/25ns
50MHz
486/Pentium
4b75066
1DH03-11-MAY95
HY6718110/111
4b75DÃ
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PDF
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diagram power supply LG 32 lh 35 fr
Abstract: No abstract text available
Text: ADVANCE M IC R O N MT58LC64K18B2 6 4 K x 18 SYNCHRONOUS SRAM I SYNCHRONOUS SRAM 64Kx 18 SRAM +3.3V SUPPLY WITH CLOCKED, REGISTERED INPUTS AND BURST COUNTER FEATURES • • • • • • • • • • • • Fast access times: 9 ,1 0 ,1 2 and 17ns Fast OE: 5 ,6 and 7ns
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MT58LC64K18B2
52-Pin
DQ12A3.
MT58LC64K18B2EJ-12
C64KI8
diagram power supply LG 32 lh 35 fr
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PDF
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93929
Abstract: No abstract text available
Text: MOTOROLA Order this document by MCM69T618/D SEMICONDUCTOR TECHNICAL DATA 64K x 18 Bit Synchronous Pipelined Cache Tag RAM MCM69T618 The MCM 69T618 is a 1 M-bit synchronous fast static RAM with integrated tag compare function. It is designed to address tag RAM for 512KB, 1MB, or 2MB
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MCM69T618/D
69T618
512KB,
512KB
93929
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PDF
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Untitled
Abstract: No abstract text available
Text: HY6718100/101 HYUNDAI 64K X 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x 18 SR A M core, address registers, data input registers, a 2-bit burst address counter and pipelined output. All synchronous inputs pass through registers controlled by a positive-edge
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OCR Scan
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HY6718100/101
486/Pentium
6ns/9ns/12ns
75MHz
486/Pentium
0DDb241
1DH01-22-MAY95
HY6718100/101
4b750flfl
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PDF
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Untitled
Abstract: No abstract text available
Text: M I CR ON T E C H N O L O G Y INC 3 SE » • bill 5 4*1 ODDEflfl? S ■ M R N ? = V á ~ 2 l-l¿ J 16K X 18 SRAM SRAM WITH ADDRESS / DATA INPUT LATCHES FEATURES • • • • • • Fast access times: 15,17,20 and 25ns Fast output enable: 6,8 and 10ns
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52-pin
T-46-23-14
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PDF
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