EP4GX230KF40C2 Search Results

sdc 606

Abstract: EP4GX230KF40C2 EP3SL150F1152C2 hsmc connector altera SOP top marking Stratix II GX FPGA Development Board Reference Manual
Text: AN 606: POS-PHY Level 4 SPI-4.2 Loopback Reference Design AN-606-1.0 May 2010 The packet over SONET/SDH physical layer (POS-PHY) Level 4—Phase 2 (SPI-4.2) loopback reference design shows how you can transmit and receive data using the Altera POS-PHY Level 4 MegaCore® function and the Stratix® IV and Stratix III