A61L73081
Abstract: A61L73081S-12 A61L73081S-15 A61L73081SW-12 A61L73081SW-15
Text: A61L73081 Series 128K X 8 BIT HIGH SPEED CMOS SRAM Document Title 128K X 8 BIT HIGH SPEED CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue July 14, 2000 Preliminary 1.0 Change ICC1 from 120mA to 220mA April 26, 2001 Final 100mA to 210mA
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A61L73081
120mA
220mA
100mA
210mA
A61L73081S-12
A61L73081S-15
A61L73081SW-12
A61L73081SW-15
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Untitled
Abstract: No abstract text available
Text: LY61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.4 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Description Initial Issue Delete Icc1 Spec. Added I Grade Spec. Revised Test Condition of ICC/ISB1/IDR Revised VTERM to VT1 and VT2
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LY61L1288
32-pin
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LY62W51216
Abstract: LY62W
Text: LY62W51216 512K X 16 BIT LOW POWER CMOS SRAM Rev. 1.3 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Description Initial Issue Added ISB Spec. Revised ICC1/ISB1/VDR/IDR Spec. Revised typos in Page 1 ICC TYP. Revised FEATURES & ORDERING INFORMATION
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LY62W51216
44-pin
48-ball
LY62W51216
LY62W
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Untitled
Abstract: No abstract text available
Text: IC62VV51216L IC62VV51216LL Document Title 512K x 16 bit 1.8V and Ultra Low Power CMOS Static RAM Revision History Revision No History Draft Date Remark 0A 0B Initial Draft November 2,2001 Preliminary 1. Remove the 55ns products September 2,2002 2. Change for ICC1: 15mA to 20mA for 70ns Industrial product
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IC62VV51216L
IC62VV51216LL
100ns
aL-70B
IC62VV51216LL-70TI
IC62VV51216LL-70BI
IC62VV51216LL-100T
IC62VV51216LL-100B
IC62VV51216LL-100TI
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Untitled
Abstract: No abstract text available
Text: A627308 Series 128K X 8 BIT CMOS SRAM Document Title 128K X 8 BIT CMOS SRAM Revision History History Issue Date Remark 0.0 Initial issue August 15, 2000 Preliminary 0.1 Omit 100ns grade items October 25, 2000 Rev. No. Change ICC1 from 70mA to 45mA Change ISB1 from 25µA to 15µA
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A627308
100ns
A627308A-S
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Untitled
Abstract: No abstract text available
Text: LY61L10248A 1M X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.3 REVISION HISTORY Revision Description Issue Date Rev. 1.0 Rev. 1.1 Initial Issued 1.“CE# ≧VCC - 0.2V” revised as ”CE# ≦0.2” for TEST CONDITION of Average Operating Power supply Current Icc1 on page3
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LY61L10248A
Page11
industry85â
LY61L10248AML-8T
LY61L10248AML-8
LY61L10248AGL-12IT
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Untitled
Abstract: No abstract text available
Text: LY611024 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.6 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.5 Description Initial Issue Delete Icc1 Spec. Add E/I grade Revised VTERM to VT1 and VT2 Revised Test Condition of ISB1/IDR Added LL Spec.
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LY611024
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K6F1616U6A
Abstract: K6F1616U6A-F
Text: K6F1616U6A Family CMOS SRAM Document Title 1M x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial draft September 11, 2001 Preliminary 1.0 Finalize - added 45ns product - changed ICC1 : 3mA to 2mA
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K6F1616U6A
55/Typ.
35/Typ.
K6F1616U6A-F
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Untitled
Abstract: No abstract text available
Text: KM616FS4010 Family CMOS SRAM Document Title 256K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial Draft April 2, 1998 Advance 1.0 Finalize - DC characteristics change ICC1 : 3mA → 4mA
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KM616FS4010
48-CSP
25/Typ.
45/Typ.
68/Typ.
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80196 architecture
Abstract: intel 80196 intel 80-196 ICC196
Text: DEVELOPMENT SOFTWARE IAR SYSTEMS SOFTWARE, INC. ICC196 Compiler Kit • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Full ANSI C Conformance Nine Levels of Chip Specific Optimizations NT/NU Extended Addressing Supported Code Banking Up to 8 MB For the K Series
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ICC196
80196 architecture
intel 80196
intel 80-196
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Untitled
Abstract: No abstract text available
Text: LY61256 32K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.3 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Description Initial Issue Delete Icc1/ ISB Spec. Adding Skinny P-DIP Revised STSOP Package Outline Dimension Lyontek Inc. reserves the rights to change the specifications and products without notice.
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LY61256
LY61256
144-bit
28-pin
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Untitled
Abstract: No abstract text available
Text: LY62L10248 1024K X 8 BIT LOW POWER CMOS SRAM Rev. 0.4 REVISION HISTORY Revision Rev. 0.1 Rev. 0.2 Rev. 0.3 Rev. 0.4 Description Initial Issue Revised ISB1, ICC1, IDR, VDR Delete -45ns Spec. Added ISB Spec. Added SL Spec. Issue Date Jan.8.2007 Nov.1.2007
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LY62L10248
1024K
-45ns
LY62L10248
608-bit
44-pin
48-ball
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Untitled
Abstract: No abstract text available
Text: LY62L10248 1024K X 8 BIT LOW POWER CMOS SRAM Rev. 0.2 REVISION HISTORY Revision Rev. 0.1 Rev. 0.2 Description Initial Issue Redvised ISB1, ICC1, IDR, VDR Delete -45ns Spec. Issue Date Jan.8.2007 Nov.1.2007 Lyontek Inc. reserves the rights to change the specifications and products without notice.
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LY62L10248
1024K
-45ns
LY62L10248
608-bit
44-pin
48-ball
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Untitled
Abstract: No abstract text available
Text: LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.7 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Rev. 1.7 Description Initial Issue Deleted Icc1 Spec. Revised Truth Table Deleted Data Retention Waveform 2 (UB & LB controlled)
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LY61L6416
48-ball
-20ns
44-pin
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EM680FU16
Abstract: No abstract text available
Text: merging Memory & Logic Solutions Inc. EM680FU16 Series Low Power, 512Kx16 SRAM Document Title 512K x16 bit Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date 0.0 Initial Draft April 12 , 2002 0.1 2’nd Draft Changed Icc, Icc1 value &
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EM680FU16
512Kx16
100ns
120ns
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Untitled
Abstract: No abstract text available
Text: A43L2616B 1M X 16 Bit X 4 Banks Synchronous DRAM Document Title 1M X 16 Bit X 4 Banks Synchronous DRAM Revision History History Issue Date Remark 0.0 Initial issue August 24, 2006 Preliminary 0.1 Change ICC1 to 70mA February 14, 2007 Rev. No. Change ICC6 to 1.5mA
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A43L2616B
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K6F8016R6D
Abstract: K6F8016R6D-F
Text: Preliminary CMOS SRAM K6F8016R6D Family Document Title 512K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial draft April 26, 2004 Preliminary 0.1 Revised - Updated DC parameters ICC1, ICC2, ISB1, IDR
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K6F8016R6D
K6F8016R6D
K6F8016R6D-F
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km681000clg-5l
Abstract: KM681000CLP-7 KM681000CLP-7L KM681000CLT-5L KM681000C KM681000CL KM681000CLI KM681000CL-L KM681000CLP7L
Text: PRELIMINARY KM681000C Family CMOS SRAM Document Title 128K x8 bit Low Power CMOS Static RAM Revision History History Draft Date Remark 0.0 Initial draft November 22, 1995 Design target 0.1 First revision - Seperate read and write at ICC, ICC1 ICC = ICC1 → Read : 15mA, Write : 35mA
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KM681000C
100ns
0820R)
km681000clg-5l
KM681000CLP-7
KM681000CLP-7L
KM681000CLT-5L
KM681000CL
KM681000CLI
KM681000CL-L
KM681000CLP7L
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K6T2016
Abstract: No abstract text available
Text: K6T2016U3M Family CMOS SRAM Document Title 128K x16 bit Low Power and Low Voltage CMOS Static RAM Revision History Revision No. History Draft Data Remark 0.0 Initial Draft October 1, 1997 Preliminary 0.1 Revise - Increased operating current ICC1 :20mA → 25mA
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K6T2016U3M
K6T2016
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A623308
Abstract: A623308M-70S A623308V-70S
Text: A623308 Series 8K X 8 BIT CMOS SRAM Document Title 8K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue July 2, 1999 Preliminary 0.1 Erase 55ns part December 14, 2000 0.2 Add –SI/SU part no. and change ICC1, Isb1 December 11, 2002
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A623308
28-pin
A623308-S
A623308-SI/SU
A623308M-70S
A623308V-70S
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Untitled
Abstract: No abstract text available
Text: K6F4016S4M Family CMOS SRAM Document Title 256K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial Draft April 2, 1998 Advance 1.0 Finalize - DC characteristics change ICC1 : 3mA → 4mA
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K6F4016S4M
48-CSP
25/Typ.
45/Typ.
68/Typ.
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icc1
Abstract: No abstract text available
Text: Po, Effi, Icc vs. freq Po, Icc1, Icc2 vs. Vcc1 70 14 8 6 Icc2 Pin=200mW Vcc1=12.5V Vcc2=12.5V Tc=25deg C Icc1 10 150 155 160 165 170 20 4 10 2 175 4 6 10 50 8 40 6 30 4 Icc2 10 Po W Po 30 6 8 10 Vcc1 (V) 12 14 10 f=175MHz Pin=200mW Vcc2=12.5V Tc=25deg C
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200mW
25deg
175MHz
163MHz
icc1
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icc3
Abstract: M57788SH 3125V m577
Text: Graph f-Po M57788SH Pout,Icc vs. freq. 12 Vcc1,2,3=12.5V, Pin=0.3W, Tc=+25deg.C Zg=Zl=50ohm 50 Po W Icc1 (A) Icc2 (A) Icc3 (A) Pout (W) 40 11 10 9 8 7 30 6 5 20 4 3 2 10 1 460 470 480 490 500 freq.(MHz) -1- 510 520 530 540 Icc1/Icc2/Icc3 (A) 60 Graph Pin-Po(fL)
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M57788SH
25deg
50ohm
490MHz
500MHz
icc3
3125V
m577
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54LS257
Abstract: SNJ54LS257BJ
Text: i DEVICE 01 INACTIVE FOR NEW DESIGN AS OF 22 SEPTEMBER 1978. USE M38510/30906B— . R E V IS I O N S DATE DESCRIPTION* LTR Add logic diagram. Revise to military format. Delete vendors CAGE 34335, 07263, and 27014. Change ICC1, ICC2> and t pLH2. C APPRO VED
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M38510/30906Bâ
MULTIPLEX8510/30906BFX
54LS257
SNJ54LS257BJ
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