74LVC05
Abstract: 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14
Text: Selector Guide for ALVC/LVC Products the leading provider of high-performance logic. From single-gate to 32-bit, IDT is your source for ALVC/LVC logic. Today’s designers are developing the most challenging telecommunications, networking and PC products ever designed
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32-bit,
compatibilit-7850
74LVC05
7400 datasheet 2-input nand gate
74LVC05A
LVC1G04
transistor x1 pv 25
inverter board design pv
74ALVC1G04
74ALVCH244
7400 nand gate series
74ALVC1G14
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PDF
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3.3v 4680
Abstract: LVCH162543A SO56-2 idt74lvch162543a
Text: LVCH162543A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER W/ 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT LVCH162543A REGISTERED TRANSCEIVER ADVANCE WITH 3-STATE OUTPUTS, INFORMATION 5 VOLT TOLERANT I/O, BUS-HOLD FEATURES: –
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Original
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IDT74LVCH162543A
16-BIT
16-BIT
250ps
MIL-STD-883,
200pF,
635mm
SO56-1)
SO56-2)
3.3v 4680
LVCH162543A
SO56-2
idt74lvch162543a
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PDF
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Untitled
Abstract: No abstract text available
Text: 3.3V CMOS 16-BIT IDT74L VCH162543A REGISTERED TRANSCEIVER ADVANCE WITH 3-STATE OUTPUTS, INFORMATION 5 VOLT TOLERANT I/O, BUS-HOLD FEATURES: D E S C R IP T IO N : - Typical - ESD > 2000V per MIL-STD-883, Method 3015; - tsK o (Output Skew) < 250ps The LVCH162543A16-bit registered transceiver is built using advanced
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OCR Scan
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16-BIT
IDT74L
VCH162543A
LVCH162543A16-bit
LVCH162543A
48-Pin
56-Pin
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PDF
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Untitled
Abstract: No abstract text available
Text: LVCH162543A 3.3V CMOS 16-BIT ADVANCE REGISTERED TRANSCEIVER INFORMATION WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD flow. The A-to-B enable CEAB must be low in order to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent lowto-high transition of LEAB puts the A latches in the storage
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OCR Scan
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IDT74LVCH162543A
16-BIT
16-BIT
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PDF
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Untitled
Abstract: No abstract text available
Text: LVCH162543A 3.3V CMOS 16-BIT ADVANCE REGISTERED TRANSCEIVER INFORMATION WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD flow. The A-to-B enable CEAB must be low in order to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent lowto-high transition of LEAB puts the A latches in the storage
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OCR Scan
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IDT74LVCH162543A
16-BIT
250ps
MIL-STD-883,
200pF,
635mm
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PDF
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