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    MACH211SP Price and Stock

    Rochester Electronics LLC MACH211SP-7VC

    IC CPLD 64MC 7.5NS 100TQFP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey MACH211SP-7VC Bulk 44
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    • 100 $6.92
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    Rochester Electronics LLC MACH211SP-10JC

    IC CPLD 64MC 10NS 44PLCC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey MACH211SP-10JC Bulk 52
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    • 100 $5.78
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    Rochester Electronics LLC MACH211SP-20VC

    EE PLD, 20NS, 64-CELL PQFP44
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey MACH211SP-20VC Bulk 67
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    • 100 $4.48
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    Lattice Semiconductor Corporation MACH211SP-10JC

    CPLD MACH 2 Family 2.5K Gates 64 MacroCells 100MHz 5V 44-Pin PLCC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Verical MACH211SP-10JC 1,483 56
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    Rochester Electronics MACH211SP-10JC 1,483 1
    • 1 $5.56
    • 10 $5.56
    • 100 $5.23
    • 1000 $4.73
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    Lattice Semiconductor Corporation MACH211SP-7VC

    CPLD MACH 2 Family 2.5K Gates 64 MacroCells 133MHz 5V 44-Pin TQFP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Verical MACH211SP-7VC 79 47
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    Rochester Electronics MACH211SP-7VC 79 1
    • 1 $6.65
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    • 100 $6.25
    • 1000 $5.65
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    MACH211SP Datasheets (60)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    MACH211SP Advanced Micro Devices High-Performance EE CMOS In-System Programmable Logic Original PDF
    MACH211SP-10 Advanced Micro Devices High-Density EE CMOS Programmable Logic Original PDF
    MACH211SP-10 Advanced Micro Devices High-Performance EE CMOS In-System Programmable Logic Original PDF
    MACH211SP-10JC Advanced Micro Devices High-Performance EE CMOS In-System Programmable Logic Original PDF
    MACH211SP-10JC Advanced Micro Devices High-Density EE CMOS Programmable Logic Original PDF
    MACH211SP-10JC Lattice Semiconductor High-Performance EE CMOS Programmable Logic Original PDF
    MACH211SP-10JC Vantis High-Performance EE CMOS Programmable Logic Scan PDF
    MACH211SP-10JI Advanced Micro Devices High-Density EE CMOS Programmable Logic Original PDF
    MACH211SP-10JI Lattice Semiconductor High-Performance EE CMOS Programmable Logic Original PDF
    MACH211SP-10VC Advanced Micro Devices High-Density EE CMOS Programmable Logic Original PDF
    MACH211SP-10VC Advanced Micro Devices High-Performance EE CMOS In-System Programmable Logic Original PDF
    MACH211SP-10VC Lattice Semiconductor High-Performance EE CMOS Programmable Logic Original PDF
    MACH211SP-10VC Vantis High-Performance EE CMOS Programmable Logic Scan PDF
    MACH211SP-12 Advanced Micro Devices High-Density EE CMOS Programmable Logic Original PDF
    MACH211SP-12 Advanced Micro Devices High-Performance EE CMOS In-System Programmable Logic Original PDF
    MACH211SP-12JC Advanced Micro Devices High-Density EE CMOS Programmable Logic Original PDF
    MACH211SP-12JC Advanced Micro Devices High-Performance EE CMOS In-System Programmable Logic Original PDF
    MACH211SP-12JC Lattice Semiconductor High-Performance EE CMOS Programmable Logic Original PDF
    MACH211SP-12JC Vantis High-Performance EE CMOS Programmable Logic Scan PDF
    MACH211SP-12JI Advanced Micro Devices High-Density EE CMOS Programmable Logic Original PDF

    MACH211SP Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    tms 3755

    Abstract: teradyne lasar HI-LO ALL-07 teradyne flex tester HP3070 MACH211SP PALCE22V10 MACHXL PALCE26V16
    Text: MACH 1 & 2 FAMILIES 1 FINAL COM’L: -7/10/12/15 IND: -10/12/14/18 MACH 1 & 2 Families MACH211SP-7/10/12/15 High-Performance EE CMOS In-System Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ JTAG-Compatible, 5-V in-system programming ◆ 44 Pins in PLCC and TQFP


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    PDF MACH211SP-7/10/12/15 PALCE26V16" MACH211SP PQT044 44-Pin 16-038-PQT-2 tms 3755 teradyne lasar HI-LO ALL-07 teradyne flex tester HP3070 PALCE22V10 MACHXL PALCE26V16

    BP1148

    Abstract: teradyne lasar tico 732 MACH210 MACH211SP PAL22V10 TEA 1020 sp
    Text: FINAL COM’L: -7.5/10/12/15/20 IND: -10/12/14/18/24 MACH211SP-7/10/12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • JTAG-Compatible, 5-V in-system programming ■ 44 Pins ■ 64 Macrocells ■ Peripheral Component Interconnect PCI


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    PDF MACH211SP-7/10/12/15/20 PAL26V16" MACH210 MACH211SP 16-038-SQ PQT044 44-Pin 16-038-PQT-2 BP1148 teradyne lasar tico 732 MACH210 PAL22V10 TEA 1020 sp

    MACH211SP

    Abstract: No abstract text available
    Text: Mixed Supply Design with MACH 1 & 2 SP Devices ABSTRACT Vantis provides robust and feature-rich I/O structures on members of its MACH 1 & 2 SP families. To make the most use of these features, it is helpful to understand their characteristics. This technical note will describe mixed supply design as it pertains to the MACH 1 & 2 SP1


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    PDF

    Untitled

    Abstract: No abstract text available
    Text: MACH 5 FAMILY 1 ADVANCE INFORMATION COM’L: -5/7/10/12 IND:-7/10/12/15 MACH5LV-192 MACH5LV-192/68-5/7/10/12 MACH5LV-192/160-5/7/10/12 MACH5LV-192/104-5/7/10/12 MACH5LV-192/120-5/7/10/12 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ Pin-, function- and JEDEC-compatible with the MACH5-192


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    PDF MACH5LV-192 MACH5LV-192/68-5/7/10/12 MACH5LV-192/160-5/7/10/12 MACH5LV-192/104-5/7/10/12 MACH5LV-192/120-5/7/10/12 MACH5-192 MACH5LV-192/XXX-7/10/12/15

    2A299

    Abstract: HP3070 MArking 3A5 AMD CPLD Mach 1 to 5 MACH5-256
    Text: MACH 5 FAMILY 1 FINAL COM’L: -7/10/12/15 IND: -10/12/15/20 MACH5-256 MACH5-256/68-7/10/12/15 MACH5-256/120-7/10/12/15 MACH5-256/104-7/10/12/15 MACH5-256/160-7/10/12/15 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ Fifth generation MACH architecture


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    PDF MACH5-256 MACH5-256/68-7/10/12/15 MACH5-256/120-7/10/12/15 MACH5-256/104-7/10/12/15 MACH5-256/160-7/10/12/15 16-038-PQR-1 PRH208 MACH5-256/XXX-7/10/12/15 2A299 HP3070 MArking 3A5 AMD CPLD Mach 1 to 5 MACH5-256

    HP3070

    Abstract: PALCE22V10
    Text: 1 FINAL MACH 1 & 2 FAMILIES COM’L: -5/7/10/12/15 IND: -7/10/12/14/18 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ 44 Pins in PLCC and TQFP ◆ 32 Macrocells ◆ 5 ns tPD Commercial, 7.5 ns tPD Industrial ◆ 182 MHz fCNT ◆ 32 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs


    Original
    PDF PALCE26V16" MACH211 MACH111 PQT044 44-Pin 16-038-PQT-2 MACH111-5/7/10/12/15 HP3070 PALCE22V10

    mach 1 family amd

    Abstract: AMD CPLD Mach 1 to 5 MACH355 22V10 PAL CMOS device mach 1 to 5 family amd
    Text: Product HIGHLIGHTS • MACH 1–5 CPLD Families ■ Fastest speeds; Easiest-to-Use ■ SpeedLocking Fixed, Guaranteed Timing ■ 32–512 Macrocells; 32–256 I/Os ■ JTAG-ISP; 3.3-V or 5-V Solutions ■ PCI-Compliance at 5, 7, 10 and 12ns ■ EECMOS Technology Leadership


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    PDF 1-888-VANTIS2 GAC-22M-7/97-0 10253R mach 1 family amd AMD CPLD Mach 1 to 5 MACH355 22V10 PAL CMOS device mach 1 to 5 family amd

    MC189

    Abstract: 9300 4b10 2D15 marking 1A15 HP 3D6 1b61a0 MACH5-320 ae 4b15
    Text: MACH 5 FAMILY 1 FINAL COM’L:-7/10/12/15 IND:-10/12/15/20 MACH5-320/MACH5LV-320 MACH5-320/120-7/10/12/15 MACH5-320/192-7/10/12/15 MACH5LV-320/184-7/10/12/15 MACH5-320/160-7/10/12/15 MACH5LV-320/120-7/10/12/15 MACH5LV-320/192-7/10/12/15 MACH5-320/184-7/10/12/15


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    PDF MACH5-320/MACH5LV-320 MACH5-320/120-7/10/12/15 MACH5-320/192-7/10/12/15 MACH5LV-320/184-7/10/12/15 MACH5-320/160-7/10/12/15 MACH5LV-320/120-7/10/12/15 MACH5LV-320/192-7/10/12/15 MACH5-320/184-7/10/12/15 MACH5LV-320/160-7/10/12/15 16-038-BGD256-1 MC189 9300 4b10 2D15 marking 1A15 HP 3D6 1b61a0 MACH5-320 ae 4b15

    4D-13

    Abstract: HP 3D6 making 5A6 3d13 3D-14 5B7 Marking i 384
    Text: MACH 5 FAMILY X FINAL COM’L:-7/10/12/15 IND:-10/12/15/20 MACH5-384/MACH5LV-384 MACH5-384/120-7/10/12/15 MACH5-384/192-7/10/12/15 MACH5LV-384/184-7/10/12/15 MACH5-384/160-7/10/12/15 MACH5LV-384/120-7/10/12/15 MACH5LV-384/192-7/10/12/15 MACH5-384/184-7/10/12/15


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    PDF MACH5-384/MACH5LV-384 MACH5-384/120-7/10/12/15 MACH5-384/192-7/10/12/15 MACH5LV-384/184-7/10/12/15 MACH5-384/160-7/10/12/15 MACH5LV-384/120-7/10/12/15 MACH5LV-384/192-7/10/12/15 MACH5-384/184-7/10/12/15 MACH5LV-384/160-7/10/12/15 16-038-BGD256-1 4D-13 HP 3D6 making 5A6 3d13 3D-14 5B7 Marking i 384

    TEA 1045

    Abstract: MACH5LV
    Text: MACH 5 FAMILY 1 ADVANCE INFORMATION COM’L: -5/7/10/12 IND: -7/10/12/15 MACH5LV-256 MACH5LV-256/68-5/7/10/12 MACH5LV-256/120-5/7/10/12 MACH5LV-256/104-5/7/10/12 MACH5LV-256/160-5/7/10/12 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ Pin-, function- and JEDEC-compatible with the MACH5-256


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    PDF MACH5LV-256 MACH5LV-256/68-5/7/10/12 MACH5LV-256/120-5/7/10/12 MACH5LV-256/104-5/7/10/12 MACH5LV-256/160-5/7/10/12 MACH5-256 MACH5LV-256/XXX-7/10/12/15 TEA 1045 MACH5LV

    HP3070

    Abstract: MACH211SP MACHXL
    Text: 1 ADVANCE INFORMATION MACH 4 FAMILY COM’L: -7/10/12/15 IND: -10/12/14/18 MACH4-64/MACH4LV-64 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 44 pins in PLCC, 44 and 48 pins in TQFP 64 macrocells


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    PDF MACH4-64/MACH4LV-64 MACH4-64/32-7/10/12/15 MACH4LV-64/32-7/10/12/15 HP3070 MACH211SP MACHXL

    HP3070

    Abstract: 1b13 107-2-A-12 MACH5 cpld amd
    Text: MACH 5 FAMILY 1 FINAL COM’L: -7/10/12/15 IND:-10/12/15/20 MACH5-192 MACH5-192/68-7/10/12/15 MACH5-192/104-7/10/12/15 MACH5-192/120-7/10/12/15 MACH5-192/160-7/10/12/15 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ Fifth generation MACH architecture


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    PDF MACH5-192 MACH5-192/68-7/10/12/15 MACH5-192/104-7/10/12/15 MACH5-192/120-7/10/12/15 MACH5-192/160-7/10/12/15 16-038-PQR-1 PQR208 MACH5-192/XXX-7/10/12/15 HP3070 1b13 107-2-A-12 MACH5 cpld amd

    HP3070

    Abstract: MACH211SP
    Text: 1 ADVANCE INFORMATION MACH 4 FAMILY COM’L: -7/10/12/15 IND: -10/12/14/18 MACH4-64/MACH4LV-64 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ 44 pins in PLCC, 44 and 48 pins in TQFP ◆ 64 macrocells ◆ ◆ ◆ ◆ ◆ ◆ ◆


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    PDF MACH4-64/MACH4LV-64 MACH4LV-64/32-10/12/14/18 HP3070 MACH211SP

    tms 3755

    Abstract: MACH110 MACH111SP MACH211SP MACHpro cpld manual
    Text: MACH 1 & 2 FAMILIES 1 MACH 1 & 2 Families MACH 1 and 2 Families High-Performance, Low Cost EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ High-performance, low-cost, electrically-erasable CMOS PLD families ◆ 32 to 128 macrocells 1250 to 5000 PLD gates


    Original
    PDF 5/6/7/10/12/15-ns 7/10/12/14/18-ns PQL100 100-Pin 16-038-PQT-2 tms 3755 MACH110 MACH111SP MACH211SP MACHpro cpld manual

    Untitled

    Abstract: No abstract text available
    Text: Mixed Supply Design with MACH 1 & 2 SP Devices ABSTRACT Vantis provides robust and feature-rich I/O structures on members of its MACH 1 & 2 SP families. To make the most use of these features, it is helpful to understand their characteristics. This technical note will describe mixed supply design as it pertains to the MACH 1 & 2 SP1


    Original
    PDF

    O-81-4

    Abstract: MACH211SP MACH110 MACH111SP PALCE22V10 MACH111SP-10JC PALCE* programming
    Text: FINAL COM’L: -5/7.5/10/12/15 IND: -7.5/10/12/14/18 MACH111SP-5/7/10/12/15 High-Density EE CMOS Programmable Logic V A N T I S The Programmable Logic Company From AMD DISTINCTIVE CHARACTERISTICS • JTAG-Compatible, 5-V in-system programming ■ Programmable power-down mode


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    PDF MACH111SP-5/7/10/12/15 PAL26V16" MACH110 MACH211SP MACH111 PQT044 44-Pin 16-038-PQT-2 O-81-4 MACH211SP MACH110 MACH111SP PALCE22V10 MACH111SP-10JC PALCE* programming

    mach210 die

    Abstract: AP-Q mach schematic mach 1 family MACH Programmer PAL 007 PAL 007 A PAL 007 c Pal programming MACH111SP
    Text: MACH 1 and 2 CPLD Families High-Performance EE CMOS Programmable Logic FEATURES ◆ ◆ ◆ ◆ ◆ ◆ ◆ High-performance electrically-erasable CMOS PLD families 32 to 128 macrocells 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages SpeedLocking – guaranteed fixed timing up to 16 product terms


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    PDF 5/10/12/15-ns 5/10/12/14/18-ns interco14, MACH221SP MACH231 MACH231SP MACH211 MACH211SP mach210 die AP-Q mach schematic mach 1 family MACH Programmer PAL 007 PAL 007 A PAL 007 c Pal programming MACH111SP

    mach 1 to 5 family amd

    Abstract: mach 1 family amd Vantis MACHpro
    Text: MACH 5 FAMILY 1 ADVANCE INFORMATION COM’L: -5/7/10/12 IND: -7/10/12/15 MACH5LV-128 MACH5LV-128/68-5/7/10/12 MACH5LV-128/104-5/7/10/12 MACH5LV-128/120-5/7/10/12 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆


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    PDF MACH5LV-128 MACH5LV-128/68-5/7/10/12 MACH5LV-128/104-5/7/10/12 MACH5LV-128/120-5/7/10/12 MACH5-128 mach 1 to 5 family amd mach 1 family amd Vantis MACHpro

    Untitled

    Abstract: No abstract text available
    Text: VAN T I S BE Y O N D PERFORMANCI-, Product Menu An AMD .om pan \ HIGHLIGHTS MACH 1 -5 CPLD Families Fastest speeds; Easiest-to-Use SpeedLocking (Fixed, Guaranteed Timing 3 2-51 2 Macrocells; 32-256 l/Os JTAG-ISP; 3 .3 -V or 5 -V Solutions PCI-Compliance at 5, 7, 10 and 12ns


    OCR Scan
    PDF 1-888-VANTIS2 CPI-9M-8/98-0 10253U

    Untitled

    Abstract: No abstract text available
    Text: FINAL COM’L : -7/10/12/15 IN D :-10/12/14/18 MACH 4-64/MACH4LV-64 B E Y O N D P E R FO R M A N C E High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 44 pins in PLCC, 44 and 48 pins in TQFP


    OCR Scan
    PDF 4-64/MACH4LV-64 zfcm32 ACH4-64/32-7/10/12/15 ACH4LV-64/32-7/10/12/15

    sp9648

    Abstract: ci pal 014
    Text: V A N B EY O N D P ER F O R M A N C E MACH 1 and 2 CPLD Families High-Performance EE CMOS Programmable Logic FEATURES High-performance electrically-erasable CMOS PLD families 32 to 128 macrocells 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages


    OCR Scan
    PDF 5/10/12/15-ns 5/10/12/14/18-ns MACH211SP MACH221 MACH221SP MACH231 MACH231SP MACH231SP MACH131SP-5YC- sp9648 ci pal 014

    2SJ 6810

    Abstract: 2sj 6815 ISP 22V10 mach211sp MACH2115P 29m16
    Text: 0 v > I u i s.11- Vantis Device Selector Guide I BEYO N D PERFO RM A N TE MACH 4 FAMILY Table 1. MACH 4 Devices1 Commercial Device Package Macrocetls (PLD Gates 1/0$ Dedicated Inputs Output Enables PT per Output FItp- JTAG(w/NO speed adder) Flops ISP troiis


    OCR Scan
    PDF -128N/64-7 -128N/64-iO -128N/64-12 -128N/64-15 LVH28/64-10 -2S6/128-12 208PQFP 256BGA 144TQFP PALCE16V8, 2SJ 6810 2sj 6815 ISP 22V10 mach211sp MACH2115P 29m16

    k019

    Abstract: 14051 mach schematic MACH111SP MACH211SP mach131 DAPQ 11
    Text: MACH 1 and 2 CPLD Families BEYOND PERFO R M A N CE High-Performance EE CMOS Programmable Logic FEATURES ♦ ♦ ♦ ♦ ♦ ♦ ♦ High-performance electrically-erasable CMOS PLD families 32 to 128 macrocells 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages


    OCR Scan
    PDF 5/10/12/15-ns 5/10/12/14/18-ns programmin14 MACH111SP MACH131 MACH131SP MACH211 MACH211SP MACH221 MACH221SP k019 14051 mach schematic DAPQ 11

    bpi400

    Abstract: teradyne flex tester tms 3755 FLEX-700 LA 7522 machpro 1,1 teradyne lasar HP3070 MACH211SP PALCE22V10
    Text: FINAL COM’L: -6/7/10/12/15 IND: -10/12/14/18 M A C H 2 1 1 S P -6 /7 /1 0 /1 2 /1 5 B E Y O N D P E R FO R M A N C E High-Performance EE CMOS In-System Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ JTAG-Compatible, 5-V in-system programming


    OCR Scan
    PDF 211SP-6/7/10/12/15 PALCE26V16" MACH21 PQT044 44-Pin 16-038-PQT-2 PQT44 MACH211SP-6/7/10/12/15 bpi400 teradyne flex tester tms 3755 FLEX-700 LA 7522 machpro 1,1 teradyne lasar HP3070 MACH211SP PALCE22V10