Untitled
Abstract: No abstract text available
Text: Integrated Integrated DeviceTechnology DeviceTechnology CPS-1848 18 Port, 48 Lane Serial RapidIO Gen2 Switch POWER MANAGEMENT | ANALOG & RF | INTERFACE & CONNECTIVITY | CLOCKS & TIMING | MEMORY & LOGIC | TOUCH & USER INTERFACE | VIDEO & DISPLAY | AUDIO FEATURES
|
Original
|
PDF
|
CPS-1848
REVE0211
|
AN3646
Abstract: E500 GPCM-16-bit MPC8572ERM 0x48000000 MPC8572E P1XX sd1rx
Text: Freescale Semiconductor Application Note Document Number: AN3646 Rev. 0, 10/2009 Booting from Serial RapidIO / PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx by Freescale Semiconductor, Inc. Austin, TX This document is an overview of how to configure
|
Original
|
PDF
|
AN3646
MPC8572E
MPC8572E
MPC8572ERM)
AN3646
E500
GPCM-16-bit
MPC8572ERM
0x48000000
P1XX
sd1rx
|
PM6352
Abstract: No abstract text available
Text: PM6352 RSE 160 34 PM Serial RapidIO Switch Element :5 The PM6352 Serial RapidIO Switch Element RSE 160 is a 16-port RapidIO switch fabric that scales to 10 Gbit/s per port, delivering an aggregate capacity of 160 Gbit/s bi-directional switching. The RSE 160
|
Original
|
PDF
|
PM6352
16-port
PMC-2050702
|
Ericsson TSR 491 628
Abstract: NT 1307c ericsson TSR 491 641 Ericsson nokia 1600 schematic diagram schematic diagram UPS active power 600 schematic diagram UPS 600 Power free marking code H02 schematic diagram UPS active power 400 tsi620-10gclv
Text: Tsi620 RapidIO Switch / RapidIO-to-PCI Bridge User Manual Preliminary October 2007 80D7000_MA001_02 Titlepage Trademarks TUNDRA is a registered trademark of Tundra Semiconductor Corporation Canada, U.S., and U.K. . TUNDRA, the Tundra logo, Tsi620, and Silicon Behind the Network, are trademarks of Tundra Semiconductor Corporation.
|
Original
|
PDF
|
Tsi620TM
80D7000
Tsi620,
Tsi620
Ericsson TSR 491 628
NT 1307c
ericsson TSR 491 641
Ericsson
nokia 1600 schematic diagram
schematic diagram UPS active power 600
schematic diagram UPS 600 Power free
marking code H02
schematic diagram UPS active power 400
tsi620-10gclv
|
Untitled
Abstract: No abstract text available
Text: RapidIO Dynamic Data Rate Reconfiguration Reference Design for Stratix IV GX Devices AN-617-1.0 Application Note The RapidIO dynamic data rate reconfiguration reference design demonstrates how to use the ALTGX_RECONFIG megafunction to reconfigure the RapidIO MegaCore®
|
Original
|
PDF
|
AN-617-1
EP4SGX230KF40C3ES
|
CSR 8510
Abstract: CSR 8510 a10 CSR 8510 v4 80KSBR200 v8 doorbell wireless doorbell 813 doorbell circuit working ADS1118 2322 156 philips doorbell
Text: Advanced Datasheet 80KSBR200 sRIO SERIAL BUFFER FLOW-CONTROL DEVICE Device Overview ◆ The IDT80KSBR200 is a high speed Serial Buffer SerB that can connect to any Serial RapidIO compliant interface. This device is built to work with any sRIO device and especially with the IDT Pre-Processing
|
Original
|
PDF
|
80KSBR200
IDT80KSBR200
IDT70K200.
72Mbit
CSR 8510
CSR 8510 a10
CSR 8510 v4
80KSBR200
v8 doorbell
wireless doorbell 813
doorbell circuit working
ADS1118
2322 156 philips
doorbell
|
AMD64
Abstract: No abstract text available
Text: RapidIO MegaCore Function Release Notes August 2006, Version 3.1.1 These release notes for the RapidIO MegaCore function contain the following information: • ■ ■ ■ ■ ■ System Requirements System Requirements New Features & Enhancements Errata Fixed in This Release
|
Original
|
PDF
|
2000/XP
32-bit,
AMD64,
EM64T
32-bit
64-bit)
AMD64
|
avalon vhdl
Abstract: AN 390 PCI-to-DDR2 SDRAM Reference Design avalon vhdl byteenable ALTERA FPGA avalon slave interface with pci master bus UART using VHDL altera PCIe to Ethernet bridge program uart vhdl fpga PCI express design PCI Interface Master Program
Text: 10. Interfacing an External Processor to an Altera FPGA ED51011-1.0 This chapter provides an overview of the options Altera provides to connect an external processor to an Altera FPGA or Hardcopy® device. These interface options include the PCI Express, PCI, RapidIO®, serial peripheral interface SPI interface or a
|
Original
|
PDF
|
ED51011-1
avalon vhdl
AN 390 PCI-to-DDR2 SDRAM Reference Design
avalon vhdl byteenable
ALTERA FPGA
avalon slave interface with pci master bus
UART using VHDL
altera PCIe to Ethernet bridge
program uart vhdl fpga
PCI express design
PCI Interface Master Program
|
Untitled
Abstract: No abstract text available
Text: RapidIO Logical I/O and Transport Layer Interface v4.1 DS242 February 15, 2007 Product Specification Introduction LogiCORE Facts The LogiCORE RapidIO™ Logical (I/O) and Transport Layer interface is optimized for Virtex™-5 LXT/SXT, Virtex-4 FX and Virtex-II Pro FPGAs, and is compliant with
|
Original
|
PDF
|
DS242
5VLX30T
4VFX20
2VP20
|
Serial RapidIO
Abstract: GT11 RocketIO
Text: .’ Serial RapidIO Physical Layer v4.1 DS293 February 15, 2007 Product Specification Introduction LogiCORE Facts The LogiCORE Serial RapidIO Physical Layer cores are fixed-netlist solutions for the RapidIO interconnect. The 1x and 4x cores are pre-implemented and fully
|
Original
|
PDF
|
DS293
Serial RapidIO
GT11
RocketIO
|
doorbell project
Abstract: doorbell circuit diagram small doorbell project ep4cgx75df27 doorbell circuit working crc verilog code 16 bit ccitt block code error management, verilog doorbell application doorbell circuit application EP2C50F484C6
Text: RapidIO MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com MegaCore Version: Document Date: 10.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
|
Original
|
PDF
|
|
Untitled
Abstract: No abstract text available
Text: 2.5Gbps to 6.25Gbps Serial RapidIO Signal Repeater 89HP0604R Product Brief Device Overview The IDT 89HP0604R is a 2.5Gbps to 6.25Gbps Repeater IC that reconditions high-speed serial data streams. The 89HP0604R contains four half-duplex data lanes, where each half-duplex lane consists of a
|
Original
|
PDF
|
25Gbps
89HP0604R
89HP0604R
25GBs
2004August
|
8-port GbE PHY
Abstract: 80KSW0003
Text: 8-Port Serial RapidIO Switch Device Overview ◆ The CPS-8, device number 80KSW0003, is a serial RapidIO switch whose functionality is central to routing packets for distribution among DSPs, processors, FPGAs, other switches, or any other sRIO-based devices. It may also be used in
|
Original
|
PDF
|
80KSW0003,
125Gbps,
25Gbps
8-port GbE PHY
80KSW0003
|
doorbell circuit application
Abstract: doorbell project MPC8548 doorbell application Doorbell Circuits AN2923 small doorbell project doorbell doorbells MPC9548
Text: Freescale Semiconductor Application Note Document Number: AN2923 Rev. 0, 09/2005 Using the Serial RapidIO Messaging Unit on PowerQUICC III by Lorraine McLuckie Freescale Semiconductor, Inc. East Kilbride, Scotland 1 Introduction This application note is provided to assist those engineers
|
Original
|
PDF
|
AN2923
MPC8548
doorbell circuit application
doorbell project
doorbell application
Doorbell Circuits
AN2923
small doorbell project
doorbell
doorbells
MPC9548
|
|
|
Tsi500
Abstract: MQS 4
Text: Tsi400 Feature Sheet Parallel RapidIO-to-PCI-X Bus Bridge Features The Tsi400 Advantage RapidIO Interface The Tundra Semiconductor Corporation Tundra Tsi400TM is a high-performance bus bridge that connects PCI and PCI-X devices to parallel-based RapidIO devices (see Figure 1). RapidIO is a new
|
Original
|
PDF
|
Tsi400TM
Tsi400
80A7300
Tsi400,
Tsi500,
Tsi500
MQS 4
|
89HP0604
Abstract: 89HP0604R
Text: 89HP0604R Product Brief 4-Channel 6.25Gbps Serial RapidIO Signal Repeater Device Overview Features Compensates for cable and PCB trace attenuation and ISI jitter Programmable receiver equalization up to 30db Programmable de-emphasis up to -8.5dB
|
Original
|
PDF
|
89HP0604R
25Gbps
300ps
P0604R
2004August
89HP0604
89HP0604R
|
CPS-1848
Abstract: CPS 1848 srio 1848 radar distance REVC0910 LTE ANTENNA GUIDE 4x4 calculator
Text: Integrated Integrated DeviceTechnology DeviceTechnology CPS-1848 18 Port, 48 Lane Serial RapidIO Gen2 Switch POWER MANAGEMENT | ANALOG & RF | INTERFACE & CONNECTIVITY | CLOCKS & TIMING | MEMORY & LOGIC | TOUCH & USER INTERFACE | VIDEO & DISPLAY | AUDIO FEATURES
|
Original
|
PDF
|
CPS-1848
REVC0910
CPS 1848
srio
1848
radar distance
REVC0910
LTE ANTENNA GUIDE
4x4 calculator
|
CPS-1848
Abstract: CPS-1616 srio Application of dsp in military sonar CPS1616 CPS 1848 4x4 calculator
Text: Integrated Integrated DeviceTechnology DeviceTechnology CPS-1616 16-Port, 16-Lane Serial RapidIO Gen 2 Switch POWER MANAGEMENT | ANALOG & RF | INTERFACE & CONNECTIVITY | CLOCKS & TIMING | STORAGE PRODUCTS | MEMORY & LOGIC | TOUCH & USER INTERFACE | VIDEO & DISPLAY | AUDIO
|
Original
|
PDF
|
CPS-1616
16-Port,
16-Lane
REVB0610
CPS-1848
srio
Application of dsp in military sonar
CPS1616
CPS 1848
4x4 calculator
|
CPS-1848
Abstract: CPS-1616 CPS 1848 CPS-6Q Tsi572
Text: IDT RapidIO Switch Feature Comparison Chart Feature CPS-1848 CPS-1616 CPS-6Q /10Q / 16 Tsi572 / 574 / 578 Serial RapidIO Specifications 2.1 2.1 6Q 10Q 8 1.3 1.3 1.3 12 16 572 574 578 1.3 1.3 1.3 1.3 Aggregate peak throughput Gbps 240 80 60 100 20 30 40 30
|
Original
|
PDF
|
CPS-1848
CPS-1616
Tsi572
03-10/MG/SS/PDF/r4v1
PORT-610
CPS-1848
CPS-1616
CPS 1848
CPS-6Q
Tsi572
|
Untitled
Abstract: No abstract text available
Text: RapidIO MegaCore Function Errata Sheet December 2006, MegaCore Function Version 7.0 This document addresses known errata and documentation issues for the Altera RapidIOTM MegaCore® function version 7.0. Errata are functional defects or errors, which may cause the RapidIO MegaCore function to
|
Original
|
PDF
|
|
pcb thermal Design guide pcb trace
Abstract: stackup TMS320TCI6486 RG142 RG178 RG316 SPRU811 RAPIDIO
Text: Application Report SPRAAT9A – February 2008 – Revised October 2009 TMS320C6472/TMS320TCI6486 Serial RapidIO Implementation Guidelines Thomas Johnson . Digital Signal Processing Solutions
|
Original
|
PDF
|
TMS320C6472/TMS320TCI6486
TMS320TCI6486/TMS320C6472
pcb thermal Design guide pcb trace
stackup
TMS320TCI6486
RG142
RG178
RG316
SPRU811
RAPIDIO
|
tms320tci6488 evm
Abstract: amc MEZZANINE* tms320tci6488 doorbell project TMS320TCI6488 alt4gxb hsmc connector C6000 an56810 tms320tci6488 evm rapidio srio
Text: RapidIO Interoperability with TI 6488 DSP Reference Design AN568-1.0 May 2009 Introduction The Altera RapidIO interoperability reference design provides a sample interface between the Altera RapidIO MegaCore® function and the Texas Instruments TMS320TCI6488
|
Original
|
PDF
|
AN568-1
TMS320TCI6488
tms320tci6488 evm
amc MEZZANINE* tms320tci6488
doorbell project
TMS320TCI6488
alt4gxb
hsmc connector
C6000
an56810
tms320tci6488 evm rapidio
srio
|
backplane cps-16
Abstract: CPS-16 80KSW0002 LN12 srio CPRI
Text: 16-Port Serial RapidIO Switch Device Overview ◆ The CPS-16, device number 80KSW0002, is a serial RapidIO switch whose functionality is central to routing packets for distribution among DSPs, processors, FPGAs, other switches, or any other sRIO-based devices. It may also be
|
Original
|
PDF
|
16-Port
CPS-16,
80KSW0002,
CPS-16
125Gbps,
25Gbps
backplane cps-16
80KSW0002
LN12
srio
CPRI
|
80KSW0004
Abstract: IDT80KSW0004
Text: 12-Port Serial RapidIO Switch Device Overview ◆ The CPS-12, device number IDT80KSW0004, is a serial RapidIO switch whose functionality is central to routing packets for distribution among DSPs, processors, FPGAs, other switches, or any other sRIO-based devices. It may also be
|
Original
|
PDF
|
12-Port
CPS-12,
IDT80KSW0004,
CPS-12
125Gbps,
25Gbps
80KSW0004
IDT80KSW0004
|
