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Microchip Technology Inc RTAX1000SL-CQ352BX512 FPGA RTAX-SL Family 1000K Logic Units 12096 Cells 581MHz 0.15um Technology 1.5V 352-Pin CQFP - Bulk (Alt: RTAX1000SL-CQ352BX)
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Avnet Americas	RTAX1000SL-CQ352BX512	Bulk			1	1 - 10 - 100 - 1000 - 10000 -	Get Quote
Microchip Technology Inc RTAX1000SL-CQ352BX3 FPGA RTAX-SL Family 1000K Logic Units 12096 Cells 581MHz 0.15um Technology 1.5V 352-Pin CQFP - Bulk (Alt: RTAX1000SL-CQ352BX)
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Avnet Americas	RTAX1000SL-CQ352BX3	Bulk			1	1 - 10 - 100 - 1000 - 10000 -	Get Quote
Microchip Technology Inc RTAX1000S-CQ352R RTAX1000S-CQ352R, Projected EOL: 2049-02-04
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Microchip Technology Inc	RTAX1000S-CQ352R			28 Weeks		1 - 10 - 100 - 1000 - 10000 -	Buy Now
Microchip Technology Inc RTAX1000SL-LG624B RTAX1000SL-LG624B, Projected EOL: 2049-02-04
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Microchip Technology Inc	RTAX1000SL-LG624B			28 Weeks		1 - 10 - 100 - 1000 - 10000 -	Buy Now
Microchip Technology Inc RTAX1000S-CGS624R RTAX1000S-CGS624R, Projected EOL: 2049-12-14
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Microchip Technology Inc	RTAX1000S-CGS624R			28 Weeks		1 - 10 - 100 - 1000 - 10000 -	Buy Now

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RTAX1000 Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
RTAX1000S-STD		Actel	Controllers, MIL-STD-1553B Bus Controller		Original	PDF

RTAX1000 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
Untitled Abstract: No abstract text available Text: Prototyping Microsemi Rad-Tolerant Devices Microsemi™ Prototyping CQFP PACKAGE Aldec RTAX-S/SL Prototyping Adaptors RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S CQ208 CCGA/LGA PACKAGE Aldec and Microsemi have joined together, offering a new, innovative,	Original	PDF	RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S CG624 CQ352 CG1152 CG1272 RTSX32SU RTSX72SU
verilog hdl code for matrix multiplication Abstract: vhdl code for pipelined matrix multiplication vhdl code hamming verilog code for matrix multiplication vhdl code for matrix multiplication vhdl code hamming edac memory Core from Libero verilog code hamming hamming code FPGA vhdl coding for hamming code Text: Application Note AC319 Using EDAC RAM for RadTolerant RTAX-S/SL and Axcelerator FPGAs Applies to EDAC Core from Libero IDE v7.2 and Newer Introduction The newest Actel designed-for-space field programmable gate array FPGA family, RTAX-S/SL, is a highperformance, high-density, antifuse-based FPGA with embedded user static RAM (SRAM). Based on the	Original	PDF	AC319 verilog hdl code for matrix multiplication vhdl code for pipelined matrix multiplication vhdl code hamming verilog code for matrix multiplication vhdl code for matrix multiplication vhdl code hamming edac memory Core from Libero verilog code hamming hamming code FPGA vhdl coding for hamming code
2KB RAM 2114 IC Abstract: RTAX1000S vhdl code for Afdx afdx RTL code for ethernet A3P400 APA300 FFF483FFH verilog code CRC generated ethernet packet vhdl code for ethernet csma cd Text: Core10/100 Ethernet Media Access Controller Product Summary • Intended Use • Ethernet Media Access Controller • Supports 10/100 Mb/s Half/Full-Duplex Operations • Supports CSMA/CD Defined by IEEE 802.3 Standard • • • • • Network Interface Features	Original	PDF	Core10/100 512-Bit 2KB RAM 2114 IC RTAX1000S vhdl code for Afdx afdx RTL code for ethernet A3P400 APA300 FFF483FFH verilog code CRC generated ethernet packet vhdl code for ethernet csma cd
verilog code for fir filter using DA Abstract: A3P1500 vhdl code of 32bit floating point adder digital FIR Filter verilog code digital FIR Filter VHDL code fir vhdl code FIR Filter verilog code vhdl code for floating point adder IQ GENERATOR CODE WITH VHDL RTAX2000 Text: CoreFIR Finite Impulse Response FIR Filter Generator Product Summary Core Deliverables • Intended Use • – Finite Impulse Response (FIR) Filter for Actel FPGAs • Key Features • – • Self-Checking – Executable Tests Generated Output against Algorithm	Original	PDF
verilog code for implementation of des Abstract: vhdl code for DES algorithm RTAX1000S rtax1000 verilog code for des vhdl code for des decryption data encryption standard vhdl wireless encrypt Text: Core3DES Product Summary Intended Use • Whenever Data Is Transmitted Across an Accessible Medium wires, wireless, etc. • E-Commerce Transactions, Where Dedicated Encryption/ Decryption Hardware Can Ease the Load on Servers Core Deliverables • Evaluation Version	Original	PDF
LGA 478 SOCKET PIN LAYOUT Abstract: RTAX2000 Text: v5.2 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg	Original	PDF	TM1019 LGA 478 SOCKET PIN LAYOUT RTAX2000
4 BIT ALU design with vhdl code using structural Abstract: RTAX1000S CORE8051 vhdl code for accumulator vhdl code for data memory 80C31 APA150-STD ASM51 R22-BH 80C31 instruction set Text: Core8051 Product Summary • Intended Use • • • Embedded System Control Communication System Control I/O Control • • • Key Features • • • • • • • • • Supported Families 100% ASM51 8051/80C31/80C51 Compatible Instruction Set 1	Original	PDF	Core8051 ASM51 8051/80C31/80C51) 4 BIT ALU design with vhdl code using structural RTAX1000S CORE8051 vhdl code for accumulator vhdl code for data memory 80C31 APA150-STD ASM51 R22-BH 80C31 instruction set
Untitled Abstract: No abstract text available Text: Advanced v0.3  RTAX-S Family FPGAs Sp e ci a l F ea t ur es f o r Sp a ce • Up to 10,752 SEU Hardened Flip-Flops Eliminate Software TMR Necessity >LET th 37 LET, GEO SEU Rate <10-10 Errors/Bit-Day • Expected SRAM Upset Rate of <10-10 Errors/Bit-Day with	Original	PDF	32-Bits 114specifications
RTAX2000 Abstract: schematic diagram 2 sc 1020 RTAX1000 RTAX250 Synplify tmr RTAX2000S Text: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case	Original	PDF	TM1019 com/documents/CQ352FPGA RTAX2000 schematic diagram 2 sc 1020 RTAX1000 RTAX250 Synplify tmr RTAX2000S
RTAX2000 Abstract: TB125 24mA-drive 352-Pin Text: RTAX-S RadTolerant FPGAs Detailed Specifications Table 2-1 • I/O Features Comparison I/O Assignment Clamp Diode Hot Insertion 5V Tolerance Input Buffer Output Buffer LVTTL No Yes No Enabled/Disabled 3.3V PCI Yes No Yes1 Enabled/Disabled LVCMOS2.5V No Yes	Original	PDF	JESD8-11) RTAX2000 TB125 24mA-drive 352-Pin
RTAX2000 Abstract: footprint cqfp 280 RTAX1000S actel cqfp 84 Text: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case	Original	PDF	TM1019 RTAX2000 footprint cqfp 280 RTAX1000S actel cqfp 84
56 pin edac connector Abstract: PCB footprint cqfp 132 Silicon Sculptor II ACTEL CCGA 624 mechanical Text: v2.0 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case	Original	PDF	TM1019 56 pin edac connector PCB footprint cqfp 132 Silicon Sculptor II ACTEL CCGA 624 mechanical
RTAX2000 Abstract: rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3 Text: v5.1 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg	Original	PDF	TM1019 RTAX2000 rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3
CG624 Abstract: SK-AX1-AX2-KITTOP AX1000-CG624 RTAX2000 RTAX1000SL-CG624 CCGA AX2000-CG624 FG484 SK-AX2-CG624-KITBTM RTAX2000S Text: Application Note AC275 CCGA to FBGA Adapter Sockets Introduction Actel recently introduced RTAX-S/L, the next generation designed-for-space antifuse Field Programmable Gate Arrays FPGAs . RTAX-S/L, with up to four million system gates, is Actel's highest density family,	Original	PDF	AC275 CG624 SK-AX1-AX2-KITTOP AX1000-CG624 RTAX2000 RTAX1000SL-CG624 CCGA AX2000-CG624 FG484 SK-AX2-CG624-KITBTM RTAX2000S

RTAX1000S-STD Abstract: fpga 1553B 1553b VHDL RTAX1000S V203M manchester verilog decoder MIL-STD-1553B FPGA vhdl code manchester encoder MIL-HDBK-1553A 553B Text: v2.0 MIL-STD-1553B Bus Controller Core1553BBC Pr od uc t S um m ary S ynt he si s and S im ul ati on S uppor t In t e n d e d Us e • Synthesis: Exemplar, Synplicity, Design Compiler, FPGA Compiler, FPGA Express • 1553B Bus Controller BC • DMA Backend Interface to External Memory	Original	PDF	MIL-STD-1553B Core1553BBC 1553B MIL-STD-1553B 128kbytes Core1553BRT RTAX1000S-STD fpga 1553B 1553b VHDL RTAX1000S V203M manchester verilog decoder MIL-STD-1553B FPGA vhdl code manchester encoder MIL-HDBK-1553A 553B
RTAX1000S Abstract: RTAX2000S CQFP352 RTAX-S jtag pull-up resistor 10K RTAX2000 RTAX-S library RAM EDAC SEU AC173 ACTEL Text: Application Note AC173 Differences Between RTAX-S/SL and Axcelerator Introduction RTAX-S/SL is Actel's latest FPGA family designed for space applications and is a derivative of the Actel Axcelerator FPGA family. The RTAX-S/SL architecture is based on Actel's multi-featured, high-density AX	Original	PDF	AC173 RTAX1000S RTAX2000S CQFP352 RTAX-S jtag pull-up resistor 10K RTAX2000 RTAX-S library RAM EDAC SEU AC173 ACTEL
RTAX1000SL Abstract: RTAX1000S RTAX1000S-SL RTAX250SL RTAX2000SL RTAX2000S RTAX250S RTAX4000S 56 pin edac connector Text: RTAX-S/SL RadTolerant FPGAs Detailed Specifications Table 2-1 • I/O Features Comparison I/O Assignment 3.3 V LVTTL Clamp Diode Hot Insertion / Cold Sparing 1 Yes 5V Tolerance Input Buffer Output Buffer No 1 Yes Enabled/Disabled Enabled/Disabled 3.3 V PCI	Original	PDF	JESD8-11) RTAX1000SL RTAX1000S RTAX1000S-SL RTAX250SL RTAX2000SL RTAX2000S RTAX250S RTAX4000S 56 pin edac connector
Untitled Abstract: No abstract text available Text: Revision 16 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)	Original	PDF	TM1019 MIL-STD-883B
actel FG484 package mechanical drawing Abstract: RTAX2000S-CQ352 actel package mechanical drawing FG484 CQ352 2-CQFP SK-AX2000-CQ352RTFG896 sk-ax FG896 rtax2000* cqfp Text: &4 3 WR )%*$ $GDSWHU 6RFNHWV July 2004 Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 CQFP to FBGA Adapter Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3	Original	PDF	CQ352 FG484 actel FG484 package mechanical drawing RTAX2000S-CQ352 actel package mechanical drawing 2-CQFP SK-AX2000-CQ352RTFG896 sk-ax FG896 rtax2000* cqfp
56 pin edac connector Abstract: RTAX1000 edac 96 pin edac connector 292 CCGA Text: v2.1 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case	Original	PDF	TM1019 56 pin edac connector RTAX1000 edac 96 pin edac connector 292 CCGA
RTAX2000 Abstract: ProASIC3 A3P250 RTAX1000S A3P125 A54SX16A A54SX32A APA075 AX125 PAR64 RTAX250S Text: CorePCI v5.41 Product Summary Synthesis and Simulation Support Intended Use • Most Flexible High-Performance PCI Offering – Synthesis: ExemplarTM, Synopsys DC / FPGA CompilerTM, and Synplicity® • Simulation: Vital-Compliant VHDL Simulators and OVI- Compliant Verilog Simulators	Original	PDF	32-Bit 64-Bit RTAX2000 ProASIC3 A3P250 RTAX1000S A3P125 A54SX16A A54SX32A APA075 AX125 PAR64 RTAX250S
CI R-Y 1028 Abstract: a gn 137 Text: Advanced v0.2  RTAX-S Family FPGAs Sp e ci a l F ea t ur es f o r Sp a ce • Up to 10,752 SEU Hardened Flip-Flops Eliminate Software TMR Necessity >LET th 37 LET, GEO SEU Rate <10-10 Errors/Bit-Day • Expected SRAM Upset Rate of <10-10 Errors/Bit-Day with	Original	PDF	32-Bits 114ersion CI R-Y 1028 a gn 137
RTAX2000S-CQ352 Abstract: No abstract text available Text: RTAX-S RadTolerant FPGAs Detailed Specifications Table 2-1 • I/O Features Comparison I/O Assignment LVTTL Clamp Diode Hot Insertion / Cold Sparing 5V Tolerance No Yes No Input Buffer Output Buffer Enabled/Disabled 1 3.3 V PCI Yes No Yes Enabled/Disabled	Original	PDF	JESD8-11) RTAX2000S-CQ352
RTAX2000 Abstract: IDTQS32X2384 352-Pin Text: Advanced v0.1  RTAX-S Family FPGAs Sp e ci a l F ea t ur es f o r Sp a ce • Up to 10,752 SEU Hardened Flip-Flops Eliminate Software TMR Necessity >LET th 37 LET, GEO SEU Rate <10-10 Errors/Bit-Day • Expected SRAM Upset Rate of <10-10 Errors/Bit-Day with	Original	PDF	32-Bits 114his RTAX2000 IDTQS32X2384 352-Pin

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RTAX1000 Search Results

RTAX1000 Price and Stock

Microchip Technology Inc RTAX1000SL-CQ352BX512

Microchip Technology Inc RTAX1000SL-CQ352BX3

Microchip Technology Inc RTAX1000S-CQ352R

Microchip Technology Inc RTAX1000SL-LG624B

Microchip Technology Inc RTAX1000S-CGS624R

RTAX1000 Datasheets (1)

RTAX1000 Datasheets Context Search

Untitled

verilog hdl code for matrix multiplication

2KB RAM 2114 IC

verilog code for fir filter using DA

verilog code for implementation of des

LGA 478 SOCKET PIN LAYOUT

4 BIT ALU design with vhdl code using structural

Untitled

RTAX2000

RTAX2000

RTAX2000

56 pin edac connector

RTAX2000

CG624

RTAX1000S-STD

RTAX1000S

RTAX1000SL

Untitled

actel FG484 package mechanical drawing

56 pin edac connector

RTAX2000

CI R-Y 1028

RTAX2000S-CQ352

RTAX2000