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Microchip Technology Inc RTAX2000SL-1CGS624E FPGA RTAX-SL Radiation-Tolerant 2M Gates 649MHz 0.15um (CMOS) Technology 1.5V 624-Pin CCGA - Bulk (Alt: RTAX2000SL-1CGS624)
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Avnet Americas	RTAX2000SL-1CGS624E	Bulk			1	1 - 10 - 100 - 1000 - 10000 -	Get Quote
Microchip Technology Inc	RTAX2000SL-1CGS624E			49 Weeks		1 - 10 - 100 - 1000 - 10000 -	Buy Now
Microchip Technology Inc RTAX2000S-1CGS624VX259 - Bulk (Alt: RTAX2000S-1CGS624V)
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Avnet Americas	RTAX2000S-1CGS624VX259	Bulk			1	1 - 10 - 100 - 1000 - 10000 -	Get Quote
Microchip Technology Inc RTAX2000S-1CGS624BX3 Radiation-Tolerant FPGA 2000000 Gates 9856Register 8I/O Bank 624-Pin CCGA - Bulk (Alt: RTAX2000S-1CGS624B)
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Avnet Americas	RTAX2000S-1CGS624BX3	Bulk			1	1 - 10 - 100 - 1000 - 10000 -	Get Quote
Microchip Technology Inc RTAX2000S-1CGS624EX507 FPGA RTAX-S Family 2M Gates 21504 Cells 649MHz 0.15um Technology 1.5V 624-Pin CCGA - Bulk (Alt: RTAX2000S-1CGS624E)
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Avnet Americas	RTAX2000S-1CGS624EX507	Bulk			1	1 - 10 - 100 - 1000 - 10000 -	Get Quote
Microchip Technology Inc RTAX2000S-CGS624VX512 - Bulk (Alt: RTAX2000S-CGS624VX)
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Avnet Americas	RTAX2000S-CGS624VX512	Bulk			1	1 - 10 - 100 - 1000 - 10000 -	Get Quote

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RTAX2000S Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
Untitled Abstract: No abstract text available Text: Prototyping Microsemi Rad-Tolerant Devices Microsemi™ Prototyping CQFP PACKAGE Aldec RTAX-S/SL Prototyping Adaptors RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S CQ208 CCGA/LGA PACKAGE Aldec and Microsemi have joined together, offering a new, innovative,	Original	PDF	RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S CG624 CQ352 CG1152 CG1272 RTSX32SU RTSX72SU
verilog hdl code for matrix multiplication Abstract: vhdl code for pipelined matrix multiplication vhdl code hamming verilog code for matrix multiplication vhdl code for matrix multiplication vhdl code hamming edac memory Core from Libero verilog code hamming hamming code FPGA vhdl coding for hamming code Text: Application Note AC319 Using EDAC RAM for RadTolerant RTAX-S/SL and Axcelerator FPGAs Applies to EDAC Core from Libero IDE v7.2 and Newer Introduction The newest Actel designed-for-space field programmable gate array FPGA family, RTAX-S/SL, is a highperformance, high-density, antifuse-based FPGA with embedded user static RAM (SRAM). Based on the	Original	PDF	AC319 verilog hdl code for matrix multiplication vhdl code for pipelined matrix multiplication vhdl code hamming verilog code for matrix multiplication vhdl code for matrix multiplication vhdl code hamming edac memory Core from Libero verilog code hamming hamming code FPGA vhdl coding for hamming code
A3P3000 Abstract: RTAX2000S-1 A3P3000-2 APA1000-STD ProASIC3 Text: Baseline ISO/IEC 10918-1 JPEG Compliance  Programmable Huffman Tables JPEG-C Baseline JPEG Codec Core two DC, two AC and  Programmable quantization tables (up to four)  Up to 4 color components (op- tionally extendable to 255 components)  Supports all possible scan confi-	Original	PDF
IEEE-1754 Abstract: leon3 processor vhdl leon3 vhdl model sparc v8 floatingpoint addition vhdl VHDL code for floating point addition processor control unit vhdl code leon3 RTAX2000S RTAX2000S-1 Text: IEEE-STD-754 Floating Point Unit GRFPU Lite / GRFPU-FT Lite CompanionCore Data Sheet GAISLER Features Description • IEEE Std 754 compliant, supporting all rounding modes and exceptions • Operations: add, subtract, multiply, divide, square-root, convert, compare, move, abs,	Original	PDF	IEEE-STD-754 64-bit IEEE-1754 leon3 processor vhdl leon3 vhdl model sparc v8 floatingpoint addition vhdl VHDL code for floating point addition processor control unit vhdl code leon3 RTAX2000S RTAX2000S-1
verilog code for fir filter using DA Abstract: A3P1500 vhdl code of 32bit floating point adder digital FIR Filter verilog code digital FIR Filter VHDL code fir vhdl code FIR Filter verilog code vhdl code for floating point adder IQ GENERATOR CODE WITH VHDL RTAX2000 Text: CoreFIR Finite Impulse Response FIR Filter Generator Product Summary Core Deliverables • Intended Use • – Finite Impulse Response (FIR) Filter for Actel FPGAs • Key Features • – • Self-Checking – Executable Tests Generated Output against Algorithm	Original	PDF
LGA 478 SOCKET PIN LAYOUT Abstract: RTAX2000 Text: v5.2 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg	Original	PDF	TM1019 LGA 478 SOCKET PIN LAYOUT RTAX2000
Untitled Abstract: No abstract text available Text: Advanced v0.3  RTAX-S Family FPGAs Sp e ci a l F ea t ur es f o r Sp a ce • Up to 10,752 SEU Hardened Flip-Flops Eliminate Software TMR Necessity >LET th 37 LET, GEO SEU Rate <10-10 Errors/Bit-Day • Expected SRAM Upset Rate of <10-10 Errors/Bit-Day with	Original	PDF	32-Bits 114specifications
RTAX2000 Abstract: schematic diagram 2 sc 1020 RTAX1000 RTAX250 Synplify tmr RTAX2000S Text: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case	Original	PDF	TM1019 com/documents/CQ352FPGA RTAX2000 schematic diagram 2 sc 1020 RTAX1000 RTAX250 Synplify tmr RTAX2000S
RTAX2000 Abstract: TB125 24mA-drive 352-Pin Text: RTAX-S RadTolerant FPGAs Detailed Specifications Table 2-1 • I/O Features Comparison I/O Assignment Clamp Diode Hot Insertion 5V Tolerance Input Buffer Output Buffer LVTTL No Yes No Enabled/Disabled 3.3V PCI Yes No Yes1 Enabled/Disabled LVCMOS2.5V No Yes	Original	PDF	JESD8-11) RTAX2000 TB125 24mA-drive 352-Pin
ECSS-E-50-12A Abstract: ECSS-E-50-12 SpaceWire Text: SpaceWire Codec with RMAP GRSPW / GRSPW-FT CompanionCore Data Sheet Features Description • Full implementation of SpaceWire standard ECSS-E-50-12A • Protocol ID extension ECSS-E-50-11 • RMAP protocol ECSS-E-50-11 • AMBA AHB back-end with DMA • Descriptor-based autonomous multi-packet	Original	PDF	ECSS-E-50-12A ECSS-E-50-11 ECSS-E-50-12A ECSS-E-50-12 SpaceWire
RTAX2000 Abstract: footprint cqfp 280 RTAX1000S actel cqfp 84 Text: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case	Original	PDF	TM1019 RTAX2000 footprint cqfp 280 RTAX1000S actel cqfp 84
56 pin edac connector Abstract: PCB footprint cqfp 132 Silicon Sculptor II ACTEL CCGA 624 mechanical Text: v2.0 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case	Original	PDF	TM1019 56 pin edac connector PCB footprint cqfp 132 Silicon Sculptor II ACTEL CCGA 624 mechanical
RTAX2000 Abstract: rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3 Text: v5.1 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg	Original	PDF	TM1019 RTAX2000 rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3
CG624 Abstract: SK-AX1-AX2-KITTOP AX1000-CG624 RTAX2000 RTAX1000SL-CG624 CCGA AX2000-CG624 FG484 SK-AX2-CG624-KITBTM RTAX2000S Text: Application Note AC275 CCGA to FBGA Adapter Sockets Introduction Actel recently introduced RTAX-S/L, the next generation designed-for-space antifuse Field Programmable Gate Arrays FPGAs . RTAX-S/L, with up to four million system gates, is Actel's highest density family,	Original	PDF	AC275 CG624 SK-AX1-AX2-KITTOP AX1000-CG624 RTAX2000 RTAX1000SL-CG624 CCGA AX2000-CG624 FG484 SK-AX2-CG624-KITBTM RTAX2000S

RTAX1000SL Abstract: RTAX1000S RTAX1000S-SL RTAX250SL RTAX2000SL RTAX2000S RTAX250S RTAX4000S 56 pin edac connector Text: RTAX-S/SL RadTolerant FPGAs Detailed Specifications Table 2-1 • I/O Features Comparison I/O Assignment 3.3 V LVTTL Clamp Diode Hot Insertion / Cold Sparing 1 Yes 5V Tolerance Input Buffer Output Buffer No 1 Yes Enabled/Disabled Enabled/Disabled 3.3 V PCI	Original	PDF	JESD8-11) RTAX1000SL RTAX1000S RTAX1000S-SL RTAX250SL RTAX2000SL RTAX2000S RTAX250S RTAX4000S 56 pin edac connector
ACTEL CCGA 1152 mechanical Abstract: AX125 AX2000 CQ208 CQ256 CS180 FG256 PQ208 Trd16 Axcelerator Family FPGAs Text: v2.8 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates	Original	PDF
Untitled Abstract: No abstract text available Text: Revision 16 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)	Original	PDF	TM1019 MIL-STD-883B
actel FG484 package mechanical drawing Abstract: RTAX2000S-CQ352 actel package mechanical drawing FG484 CQ352 2-CQFP SK-AX2000-CQ352RTFG896 sk-ax FG896 rtax2000* cqfp Text: &4 3 WR )%*$ $GDSWHU 6RFNHWV July 2004 Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 CQFP to FBGA Adapter Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3	Original	PDF	CQ352 FG484 actel FG484 package mechanical drawing RTAX2000S-CQ352 actel package mechanical drawing 2-CQFP SK-AX2000-CQ352RTFG896 sk-ax FG896 rtax2000* cqfp
leon3 Abstract: RTAX2000 LEON3FT STK4050II vhdl code CRC ECSS-E-ST-50-11C ahb fsm KEY Component for MIL-STD-1553 IP Core for FPGA APB VHDL code AMBA ahb bus protocol Text: SpaceWire CODEC with RMAP GRSPW / GRSPW-FT CompanionCore Data Sheet GAISLER Features Description • Full implementation of SpaceWire standard ECSS-E-ST-50-12C • Protocol ID extension ECSS-E-ST-50-11C • RMAP protocol ECSS-E-ST-50-11C • AMBA AHB back-end with DMA	Original	PDF	ECSS-E-ST-50-12C ECSS-E-ST-50-11C leon3 RTAX2000 LEON3FT STK4050II vhdl code CRC ECSS-E-ST-50-11C ahb fsm KEY Component for MIL-STD-1553 IP Core for FPGA APB VHDL code AMBA ahb bus protocol
56 pin edac connector Abstract: RTAX1000 edac 96 pin edac connector 292 CCGA Text: v2.1 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case	Original	PDF	TM1019 56 pin edac connector RTAX1000 edac 96 pin edac connector 292 CCGA
RTAX2000 Abstract: ProASIC3 A3P250 RTAX1000S A3P125 A54SX16A A54SX32A APA075 AX125 PAR64 RTAX250S Text: CorePCI v5.41 Product Summary Synthesis and Simulation Support Intended Use • Most Flexible High-Performance PCI Offering – Synthesis: ExemplarTM, Synopsys DC / FPGA CompilerTM, and Synplicity® • Simulation: Vital-Compliant VHDL Simulators and OVI- Compliant Verilog Simulators	Original	PDF	32-Bit 64-Bit RTAX2000 ProASIC3 A3P250 RTAX1000S A3P125 A54SX16A A54SX32A APA075 AX125 PAR64 RTAX250S
CI R-Y 1028 Abstract: a gn 137 Text: Advanced v0.2  RTAX-S Family FPGAs Sp e ci a l F ea t ur es f o r Sp a ce • Up to 10,752 SEU Hardened Flip-Flops Eliminate Software TMR Necessity >LET th 37 LET, GEO SEU Rate <10-10 Errors/Bit-Day • Expected SRAM Upset Rate of <10-10 Errors/Bit-Day with	Original	PDF	32-Bits 114ersion CI R-Y 1028 a gn 137
RTAX2000S-CQ352 Abstract: No abstract text available Text: RTAX-S RadTolerant FPGAs Detailed Specifications Table 2-1 • I/O Features Comparison I/O Assignment LVTTL Clamp Diode Hot Insertion / Cold Sparing 5V Tolerance No Yes No Input Buffer Output Buffer Enabled/Disabled 1 3.3 V PCI Yes No Yes Enabled/Disabled	Original	PDF	JESD8-11) RTAX2000S-CQ352
RTAX2000S Abstract: LEON3FT sparc v8 FLOATING POINT Co Processor Text: ^ LEON3-FT G A IS L E R R E S E A R C H RTAX2000S nçter Introduction The LE0N3-FT processor is available as a standard component using the Actel RTAX2000S Field Programmable Gate Array. The fault tolerant design of the processor in combination with the radiation tolerant	OCR Scan	PDF	RTAX2000S RTAX2000S 32-bit 30DMIPS CQ352B LEON3FT sparc v8 FLOATING POINT Co Processor

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RTAX2000S Price and Stock

Microchip Technology Inc RTAX2000SL-1CGS624E

Microchip Technology Inc RTAX2000S-1CGS624VX259

Microchip Technology Inc RTAX2000S-1CGS624BX3

Microchip Technology Inc RTAX2000S-1CGS624EX507

Microchip Technology Inc RTAX2000S-CGS624VX512

RTAX2000S Datasheets Context Search

Untitled

verilog hdl code for matrix multiplication

A3P3000

IEEE-1754

verilog code for fir filter using DA

LGA 478 SOCKET PIN LAYOUT

Untitled

RTAX2000

RTAX2000

ECSS-E-50-12A

RTAX2000

56 pin edac connector

RTAX2000

CG624

RTAX1000SL

ACTEL CCGA 1152 mechanical

Untitled

actel FG484 package mechanical drawing

leon3

56 pin edac connector

RTAX2000

CI R-Y 1028

RTAX2000S-CQ352

RTAX2000S