XC95288-15HQ208I
Abstract: XC95288
Text: Product Obsolete/Under Obsolescence XC95288 In-System Programmable CPLD R DS069 v5.0 May 17, 2013 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates
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XC95288
DS069
36V18
XCN11010
XC95288-15HQ208I
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10HQ
Abstract: XC95288 471 E25 HQ208 XC9500
Text: XC95288 In-System Programmable CPLD September 15, 1999 Version 4.0 5* Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins
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XC95288
36V18
HQ208
208-Pin
BG352
352-Pin
XC95288
10HQ
471 E25
XC9500
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A23 780-4
Abstract: 471 E25 BG352 HQ208 XC9500 XC95288
Text: XC95288 In-System Programmable CPLD November 12, 1997 Version 2.0 3* Preliminary Product Specification Features MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f • • • • • Where: • • • • • • • • • • • MCHP = Macrocells in high-performance mode
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XC95288
arcAC25,
HQ208
208-Pin
BG352
352-Pin
XC95288
A23 780-4
471 E25
XC9500
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XC95288
Abstract: BG352 HQ208 XC9500
Text: XC95288 In-System Programmable CPLD January, 1997 Version 1.0 Advanced Product Specification Features Description • 10 ns pin-to-pin logic delays on all pins • fCNT to 111 MHz • 288 macrocells with 6,400 usable gates • Up to 192 user I/O pins
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XC95288
36V18
HQ208
208-Pin
BG352
352-Pin
XC95288
XC9500
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XC95288
Abstract: BG352 HQ208 XC9500 X5906 X7131 HQ208I
Text: 1 XC95288 In-System Programmable CPLD December 4, 1998 Version 3.0 1 1* Product Specification Features Power Management • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins
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XC95288
36V18
HQ208
208-Pin
BG352
352-Pin
XC95288
XC9500
X5906
X7131
HQ208I
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xc95288
Abstract: BG352 XC95288-20HQ208C XC95288-20HQ208
Text: XC95288 In-System Programmable CPLD R DS069 v4.0 June 18, 2003 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable
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XC95288
DS069
36V18
p352-ball
208-pin
352-ball
352-ball
BG352
XC95288-20HQ208C
XC95288-20HQ208
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XC95288
Abstract: BG352 HQ208 XC9500 n439
Text: XC95288 In-System Programmable CPLD R DS069 v4.1 August 21, 2003 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable
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XC95288
DS069
36V18
BG352
352-ball
XC95288-20HQ208I
HQ208
208-pin
XC95288-20BG352I
BG352
HQ208
XC9500
n439
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471 E25
Abstract: xc95288 XC95288-15HQ208I AD9318 A23 780-4 BG352 HQ208 XC9500 h3144 n439
Text: XC95288 In-System Programmable CPLD R DS069 v4.3 April 3, 2006 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable
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XC95288
DS069
36V18
471 E25
XC95288-15HQ208I
AD9318
A23 780-4
BG352
HQ208
XC9500
h3144
n439
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XC95288
Abstract: Marking af1 AF24 marking
Text: XC95288 In-System Programmable CPLD R DS069 v4.2 April 15, 2005 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable
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XC95288
DS069
36V18
Marking af1
AF24 marking
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XC95216-20PQG160I
Abstract: XC95216-15PQ160I 471 E25 XC95216 Family XC95216-10PQ160C XC95216-10PQ160I XC95216-15PQG160C XC95216-15PQG160I XC95216-10PQG160I XC9500
Text: XC95216 In-System Programmable CPLD R 5 Note: The 352-pin BGA packages are being discontinued for XC95216 devices. You cannot order these packages after May 14, 2008. Xilinx recommends replacing XC95216 in 352-pin BGA packages with XC95288 devices in 352-pin BGA packages in all designs as soon as possible. Recommended replacements are pin compatible, but
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XC95216
352-pin
XC95288
XCN07010
352-pin
XC95216-20PQG160I
XC95216-15PQ160I
471 E25
XC95216 Family
XC95216-10PQ160C
XC95216-10PQ160I
XC95216-15PQG160C
XC95216-15PQG160I
XC95216-10PQG160I
XC9500
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XC9500XL
Abstract: XC95144 XC95288 XC9500 XC95288 Family
Text: The FastFLASH XC9500XL Advantage .you can rest The XC9500XL 3.3V CPLD family uniquely excels in all three ARM criteria, and offers the highest level of programming reliability in a JTAGcompatible, in-system programmable family. The XC9500XL family features:
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XC9500XL
54-input
256-macrocell
XC9500
XC95144
XC95288
128-macrocell
XC95288 Family
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XC9536-PC44
Abstract: xc9572 data sheet XC9500 XC95108 XC95216 XC95288 XC9536 XC9572 HQ208 PC44
Text: Ann Duft Xilinx, Inc. 408 879-4726 [email protected] Frankie Borison Oak Ridge Public Relations (408) 253-5042 [email protected] FOR IMMEDIATE RELEASE XILINX SHIPPING LARGEST MEMBER OF ISP CPLD FAMILY SAN JOSE, Calif., August 6, 1997—Xilinx, Inc., (NASDAQ:XLNX), today announced it has begun
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1997--Xilinx,
XC9500
XC9536,
XC9572,
XC95108,
XC95216
XC95288
XC9536-PC44
xc9572 data sheet
XC95108
XC9536
XC9572
HQ208
PC44
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PQFP160 XILINX
Abstract: XC9536-44 plcc44 pinout numbers XC9500 pinout tas t23 Fuse n25 PLCC44 pinout PLCC84 package VQFP44 package XC9500 Family
Text: XILINX PROGRAMMER QUALIFICATION SPECIFICATION XC9500 FAMILY Introduction This document pertains to the following devices and packages: device addresses are contained on the included Add.dat floppy disk. Signature String 9536 - PLCC44, CSP48, and VQFP44 9572 - PLCC44, PLCC84, PQFP100,
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XC9500
PLCC44,
CSP48,
VQFP44
PLCC84,
PQFP100,
TQFP100
PQFP160 XILINX
XC9536-44
plcc44 pinout numbers
XC9500 pinout
tas t23
Fuse n25
PLCC44 pinout
PLCC84 package
VQFP44 package
XC9500 Family
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jtag 14
Abstract: XC9500XL
Text: by Dave Chiang, Manager, CPLD Technical Marketing, david.chiang@ xilinx.com Choosing A 3.3V CPLD? ARM Yourself
Leading digital system manufacturers are rapidly adopting 3.3V components for higher performance, lower costs, lower power, and higher system reliability. With many new 3.3V
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256-macrocell
XC9500
XC95144
XC95288
128-macrocell
256-macrocell
XC95288
jtag 14
XC9500XL
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100-PIN TQFP XILINX DIMENSION
Abstract: xilinx xc9536 digital clock xc9536-pc44 XC95216XL xc95144 pin diagram XC95108XL XC9536 XC95144 XC9500 pinout XC9536XL Series
Text: Ann Duft Xilinx, Inc. 408 879-4726 [email protected] Kathy Keller Oak Ridge Public Relations (408) 253-5042 [email protected] FOR IMMEDIATE RELEASE XILINX ANNOUNCES NEWEST MEMBER OF INDUSTRY’S FASTEST GROWING CPLD FAMILY New XC95144 device targets sweet spot of ISP CPLD market with lowest price per macrocell
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XC95144
1998--Xilinx,
XC9500
100-PIN TQFP XILINX DIMENSION
xilinx xc9536 digital clock
xc9536-pc44
XC95216XL
xc95144 pin diagram
XC95108XL
XC9536
XC9500 pinout
XC9536XL Series
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XC9500 pinout
Abstract: AC24-AC25 Fuse n25 xilinx xc9536 XC9500 XC95108 XC95144 XC95216 XC95288 XC9536
Text: XILINX PROGRAMMER QUALIFICATION SPECIFICATION XC9500 FAMILY Introduction Signature String The device programming and verification procedures are similar to those used with standard FLASH EPROM memories. Initially, and after each erasure, all cells in the device
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XC9500
XC9500 pinout
AC24-AC25
Fuse n25
xilinx xc9536
XC95108
XC95144
XC95216
XC95288
XC9536
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XC95144
Abstract: DS06 HW130 XC9500 XC95108 XC95216 XC95288 XC9536 XC9572 xc95144 pinout
Text: k XC9500 In-System Programmable CPLD Family R DS063 v5.1 September 22, 2003 Product Specification Features - Advanced CMOS 5V Fast FLASH technology • - Supports parallel programming of multiple XC9500 devices • High-performance - 5 ns pin-to-pin logic delays on all pins
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XC9500
DS063
XC9500
36V18
Func500
XC95288.
XC95144
DS06
HW130
XC95108
XC95216
XC95288
XC9536
XC9572
xc95144 pinout
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AC1284
Abstract: No abstract text available
Text: KXILINX XC95288 In-System Programmable CPLD April, 1997 Version 1.0 Preliminary Product Specification Features Description • 15 ns pin-to-pin logic delays on all pins • • • • fcNT t ° MHz 288 macrocells with 6,400 usable gates Up to 192 user I/O pins
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XC95288
36V18
HQ208
208-Pin
BG352
352-Pin
XC95288
AC1284
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XC95288
Abstract: No abstract text available
Text: flXIUNX XC95288 In-System Programmable CPLD December 4, 1998 Version 3.0 Product Specification Features Power Management • • 15 ns pin-to-pin logic delays on all pins fcN T 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins
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XC95288
36V18
HQ208
208-Pin
BG352
352-Pin
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F25-F26
Abstract: No abstract text available
Text: flXILINX XC95288 In-System Programmable CPLD N o vem b er 12, 1997 V ersion 2.0 Preliminary Product Specification Features MCHp (1.7) + MC lp (0.9) + MC (0.006 mA/MHz) f • 15 ns pin-to-pin logic delays on all pins • fcNT 95 MHz • 288 macrocells with 6,400 usable gates
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XC95288
36V18
HQ208
208-Pin
BG352
352-Pin
F25-F26
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RES 364
Abstract: XC95288
Text: HXILINX XC9500 Series Table of Contents XC9500 In-System Programmable CPLD Family F eatu res. Family O verview .
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XC9500
XC95288
RES 364
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XC95288
Abstract: XC952 cpld xc9572
Text: flXILINX XC9500 Series Table of Contents XC9500 In-System Programmable CPLD Family F eatu res. D escription.
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XC9500
XC95576
XC95288
XC952
cpld xc9572
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XC95288
Abstract: No abstract text available
Text: flXIU N X XC95286 In-System Programmable CPLD October 28, 1997 Version 2.0 Preliminary Product Specification Features MC h p (1.7) + MC lp (0.9) + MC (0.006 m A/M Hz) f • 15 ns pin-to-pin logic delays on all pins Where: • • • • fcNT to MHz 288 macrocells with 6,400 usable gates
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XC95286
36V18
boundary-scaE15,
XC95288
HQ208
208-Pin
BG352
352-Pin
XC95288
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Untitled
Abstract: No abstract text available
Text: flX IU N X XC95286 In-System Programmable CPLD November 12, 1997 Version 2.0 Preliminary Product Specification Features MC h p (1.7) + MC lp (0.9) + MC (0.006 m A/M Hz) f • 15 ns pin-to-pin logic delays on all pins Where: • • • • fcNT to MHz 288 macrocells with 6,400 usable gates
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XC95286
36V18
XC95288
HQ208
208-Pin
BG352
352-Pin
XC95288
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