CY7C1046BV33
Abstract: CY7C1046BV33-10VC CY7C1046BV33-12VC CY7C1046BV33-15VC
Text: 046BV33 PRELIMINARY 7C1046BV33 1M x 4 Static RAM Features • High speed — tAA = 10 ns • Low active power for 10 ns speed — 540 mW max. • Low CMOS standby power (L version) — 1.8 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected
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046BV33
CY7C1046BV33
CY7C1046BV33
CY7C1046BV33-10VC
CY7C1046BV33-12VC
CY7C1046BV33-15VC
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Untitled
Abstract: No abstract text available
Text: 7C1046D 4-Mbit 1 M x 4 Static RAM 4-Mbit (1 M × 4) Static RAM Features Functional Description The 7C1046D[1] is a high-performance CMOS static RAM organized as 1M words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW
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CY7C1046D
CY7C1046D
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CY7C1046BV33
Abstract: CY7C1046BV33-10VC CY7C1046BV33-12VC CY7C1046BV33-15VC
Text: 33 PRELIMINARY 7C1046BV33 1M x 4 Static RAM Features • High speed — tAA = 10 ns • Low active power for 10 ns speed — 540 mW max. • Low CMOS standby power (L version) — 1.8 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected
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CY7C1046BV33
CY7C1046BV33
CY7C1046BV33-10VC
CY7C1046BV33-12VC
CY7C1046BV33-15VC
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CY7C1046V33
Abstract: CY7C1046V33-12VC CY7C1046V33-15VC
Text: 3 ADVANCE INFORMATION 7C1046V33 1M x 4 Static RAM Features • High speed — tAA = 10 ns • Low active power for 10 ns speed — 540 mW max. • Low CMOS standby power (L version) — 1.8 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention)
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CY7C1046V33
CY7C1046V33
CY7C1046V33-12VC
CY7C1046V33-15VC
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CY7C1046
Abstract: 7c1046
Text: ADVANCED INFORMATION 7C1046 1M x 4 Static RAM Features • High speed — tAA = 10 ns • Low active power — 1018 mW max. • Low CMOS standby power(L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected
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CY7C1046
CY7C1046
7c1046
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Untitled
Abstract: No abstract text available
Text: 7C1046D 4-Mbit 1M x 4 Static RAM Functional Description[1] Features • Pin- and function-compatible with 7C1046B • High speed — tAA = 10 ns • CMOS for optimum speed/power • Low active power — ICC = 90 mA @ 10 ns • Low CMOS Standby Power
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CY7C1046D
CY7C1046B
400-mil-wide
32-pin
CY7C1046D
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CY7C1046B
Abstract: CY7C1046B-12VC CY7C1046B-15VC CY7C1046B-20VC
Text: 7C1046B 7C1046B 1M x 4 Static RAM Features • High speed — tAA = 12 ns • Low active power — 935 mW max. • Low CMOS standby power (L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected
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1CY7C1046B
CY7C1046B
CY7C1046B
CY7C1046B-12VC
CY7C1046B-15VC
CY7C1046B-20VC
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CY7C1046D-10VXI
Abstract: V324 CY7C1046B CY7C1046D
Text: 7C1046D 4-Mbit 1M x 4 Static RAM Functional Description[1] Features • Pin- and function-compatible with 7C1046B • High speed — tAA = 10 ns • CMOS for optimum speed/power • Low active power — ICC = 90 mA @ 10 ns • Low CMOS Standby Power
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CY7C1046D
CY7C1046B
CY7C1046D
CY7C1046D-10VXI
V324
CY7C1046B
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CY7C1046B
Abstract: CY7C1046B-12VC CY7C1046B-15VC CY7C1046B-20VC 046b
Text: 046B 7C1046B 1M x 4 Static RAM Features • High speed — tAA = 12 ns • Low active power — 935 mW max. • Low CMOS standby power (L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected
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CY7C1046B
CY7C1046B
CY7C1046B-12VC
CY7C1046B-15VC
CY7C1046B-20VC
046b
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CY7C1046BV33
Abstract: CY7C1046BV33-10VC CY7C1046BV33-12VC CY7C1046BV33-15VC
Text: 046BV33 PRELIMINARY 7C1046BV33 1M x 4 Static RAM Features • High speed — tAA = 10 ns • Low active power for 10 ns speed — 540 mW max. • Low CMOS standby power (L version) — 1.8 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected
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046BV33
CY7C1046BV33
CY7C1046BV33
CY7C1046BV33-10VC
CY7C1046BV33-12VC
CY7C1046BV33-15VC
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Untitled
Abstract: No abstract text available
Text: 7C1046D 4-Mbit 1 M x 4 Static RAM 4-Mbit (1 M × 4) Static RAM Features Functional Description • Pin- and function-compatible with 7C1046B The 7C1046D is a high-performance CMOS static RAM organized as 1M words by 4 bits. Easy memory expansion is
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CY7C1046D
CY7C1046D
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CY7C1046B-15VC
Abstract: CY7C1046B CY7C1046B-12VC
Text: ADVANCE INFORMATION 7C1046B 1M x 4 Static RAM Features • High speed — tAA = 10 ns • Low active power — 1018 mW max. • Low CMOS standby power (L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected
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CY7C1046B
CY7C1046B
CY7C1046B-15VC
CY7C1046B-12VC
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V324
Abstract: CY7C1046B CY7C1046D CY7C1046D-10VXI
Text: 7C1046D 4-Mbit 1M x 4 Static RAM Functional Description[1] Features • Pin- and function-compatible with 7C1046B • High speed — tAA = 10 ns • CMOS for optimum speed/power • Low active power — ICC = 90 mA @ 10 ns • Low CMOS Standby Power
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CY7C1046D
CY7C1046B
CY7C1046D
V324
CY7C1046B
CY7C1046D-10VXI
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1046B-2
Abstract: 1046b8
Text: 7C1046BN 1M x 4 Static RAM Features You write to the device by taking Chip Enable CE and Write Enable (WE) inputs LOW. Data on the four IO pins (IO0 through IO3) is then written into the location specified on the address pins (A0 through A19). • Low active power
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CY7C1046BN
32-pin
CY7C1046BN
1046B-2
1046b8
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Untitled
Abstract: No abstract text available
Text: 7C1046D 4-Mbit 1 M x 4 Static RAM 4-Mbit (1 M × 4) Static RAM Features provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable
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CY7C1046D
CY7C1046B
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4946
Abstract: CY7C1041B CY7C1046B CY7C1049B JESD22 MIL-STD-883 PRESSURE COOKER
Text: Cypress Semiconductor Product/Technology Qualification Report QTP# 000301 VERSION 1.0 May, 2000 4 Meg Asynchronous RAM R52D-5R Technology, Fab 4 CY7C1041B 256K x 16 Static RAM 7C1046B 1M x 4 Static RAM CY7C1049B 512K x 8 Static RAM CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA:
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R52D-5R
CY7C1041B
CY7C1046B
CY7C1049B
CY7C149B
CY7C1049B-VC
4946
CY7C1041B
CY7C1046B
CY7C1049B
JESD22
MIL-STD-883 PRESSURE COOKER
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CY7C1046BN
Abstract: CY7C1046BN-15VC
Text: 7C1046BN 1M x 4 Static RAM Features You write to the device by taking Chip Enable CE and Write Enable (WE) inputs LOW. Data on the four IO pins (IO0 through IO3) is then written into the location specified on the address pins (A0 through A19). • Low active power
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CY7C1046BN
32-pin
CY7C1046BN
CY7C1046BN-15VC
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CY7C1046B
Abstract: CY7C1046B-12VC CY7C1046B-15VC CY7C1046B-20VC
Text: 046B 7C1046B 1M x 4 Static RAM Features • High speed — tAA = 12 ns • Low active power — 935 mW max. • Low CMOS standby power (L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected
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CY7C1046B
CY7C1046B
CY7C1046B-12VC
CY7C1046B-15VC
CY7C1046B-20VC
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Untitled
Abstract: No abstract text available
Text: V CYPRESS 1M x 4 Static RAM Features sion is provided by an active LOW Chip Enable CE , an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four I/O pins (I/Oq
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CY7C1046V33
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